Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.
So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.
Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.
Using high-speed can significantly solve this issue.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds general board files based on MT7981 SoCs.
MT7981 uses one mmc controller for booting from both SD and eMMC, and the
pins of mmc controller are also shared with spi controller.
So three configs are need for these boot types:
1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND
2. mt7981_emmc_rfb_defconfig - eMMC only
3. mt7981_sd_rfb_defconfig - SD only
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add general board files based on MT7986 SoCs.
MT7986 uses one mmc controller for booting from both SD and eMMC.
Both MT7986A and MT7986B use the same pins for spi controller.
Configs for various boot types:
1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B
2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only
3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds basic support for MediaTek MT7981 SoC.
This include the file that will initialize the SoC after boot and its
device tree.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds basic support for MediaTek MT7986 SoC.
This include the file that will initialize the SoC after boot and its
device tree.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.
With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c ("ram:
stm32mp1: compute DDR size from DDRCTL registers").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change the mask of OTP0 used to close the device on STM32MP
- STM32MP15x: bit 6 of OPT0
- STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
And support the 2 keys for STM32MP13x
- PKHTH : Hash of the 8 ECC Public Keys Hashes Table
(ECDSA is the authentication algorithm)
- EDMK : Encryption/Decryption Master Key
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Update the command stm32key to support several keys selected by
key name and managed by the new sub-command:
stm32key list
stm32key select [<key>]
stm32key read -a
This patch doesn't change the STM32MP15 behavior, only PKH is
supported, but it is a preliminary patch for STM32MP13 support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Split the read_hash_otp function and introduce the helper function
read_close_status to read the close status in OTP separately of the PKH.
This patch is a preliminary step for STM32MP13 support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add defines for value used in stm32key for BSEC permanent lock status
and error.
This patch is a preliminary step to support more lock status in BSEC
driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Improve the partitioning trace done in command stm32prog:
- remove the trace "partition: Done" when the GPT partitioning is not done
- indicate the mmc instance used for each 'gpt write' command
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
As the SMC is only supported in SP-MIN for STM32MP15x, the associated
partition should be absent when the TA NVMEM is not available in OPT-TEE
in STM32MP13x.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Solve many compilation warning when stm32prog is activated on the aarch64.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change the defaut flashlayout location, hardcoded at STM32_DDR_BASE,
to CONFIG_SYS_LOAD_ADDR to avoid issue on board with reserved memory
at STM32_DDR_BASE.
This patch changes the command behavior for STM32MP13 and STM32MP15
platform, as CONFIG_SYS_LOAD_ADDR(0xc2000000) != STM32_DDR_BASE
but without impact for serial boot with STM32CubeProgrammer.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
When the STM32CubeProgrammer sent a empty flashlayout.tsv
file, the command stm32prog correctly parse the file
but data->dev_nb = 0 and the stm32prog_devices_init
operations should be skipped.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset. Reset description will be added in separate commit.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.
Fixes: 24a7a3c1c0 ("imx8mm: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.
Fixes: e0caa84ca6 ("imx8mp: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmMoEdgcHGV1Z2VuLmhy
aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyNvEB/4nEeiBx7Lo1gK+79PJ
9kCUngglHRu3/+FJMpcOp+2b6sSW1IZs8qGBMAMFSRoFElrLMMbVEgBR0ZfJCl3c
It0xN9Buhe8muwtAdE8Amr4PddUEynzglVPpFUFfir6ZqFAcedmN6iuh+K82r7Be
7s/8tRb2hVp//TpkEntf2yxrYnyeW4qiXyUxbUhaUyyhkM3RBXySuY4qnaaLp3NY
R9rsIY5j3kA2QylebEamlXI+KDvszrGbkUOUUrlwkygQNR/GmAYQPlY1TdBwk0wE
U1CO8zQYaL3OY998lU32pMVClmwyXbn2i7KAyMm3TEgrfpjQsLTS2BK+w+RBdMGL
XGnt
=lRvM
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-2023.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.01 cycle:
This feature set includes the important update on PIO4 pinctrl driver
that solves a long time mismatch between Linux and U-boot, related on
the unification of pinctrl and gpio driver support, now respecting the
pinctrl bindings ABI; and also support for pinctrl subnodes. The feature
set also adds support for PDA screen detection for sam9x60_curiosity
board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
Adding the "u-boot,dm-pre-reloc" DT property to the timer node is
necesssary to support the timer in the early boot phases (e.g.
SPL & pre-reloc).
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Add the DT bindings / descriptions for timer0 & timer1, exactly as done
in mainline Linux.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
This patch changes the compilation, so that the Armada 375 board(s) are
compiled in a separate step. This is necessary for the timer dts
conversion, as A375 has a different / timer description in the dts.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Now that the new timer support is available for these platforms, let's
select this IF for all these platforms. This way it's not necessary
that each board changes it's config header.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
With the recent changes in the Marvel mvneta network driver, the MDIO
bus is not connected any more. This patch updates the DT nodes to use
the nodes from the dtsi files instead of creating ad-hoc nodes.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch makes sure that the Devicetree for the sama7
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
This patch makes sure that the Devicetree for the sama5
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
the I2C5 GPIOs are on gpio3 instead of gpio5.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since
this file is shared by PDK2, PicoITX and DRC02. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
This PHY is not used on PDK2, the header was added due to copy-paste
error, drop it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Add information about which exact SoM variant is used on which PDK2 variant.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Adam Ford <aford173@gmail.com>
Fix spurious ampersand in address print e.g.
Find img info 0x&480331a0, size 855
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>"
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
SDRAM
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
We currently have an if_type (interface type) and a uclass id. These are
closely related and we don't need to have both.
Drop the if_type values and use the uclass ones instead.
Maintain the existing, subtle, one-way conversion between UCLASS_USB and
UCLASS_MASS_STORAGE for now, and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable this option on all boards which support block devices. Drop the
related depencies on BLK since these are not needed anymore.
Disable BLOCK_CACHE on M5253DEMO as this causes a build error.
Signed-off-by: Simon Glass <sjg@chromium.org>
* Remove unnecessary device tree nodes which are not needed in
U-Boot directly.
* Move all U-Boot specific device tree properties to u-boot dtsi.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Commit 6337d53fdf ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs
the am335x device tree with the latest linux kernel am335x device tree.
That causes problems with device tree in SPL stage.
To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the
synced bus addresses correctly.
A custom U-Boot device tree is also needed since the SPL build removes
bus properties from bus nodes which are not explicitly marked with the
u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of
the in the SPL needed devices must be marked with u-boot,dm-pre-reloc.
Also since there is no driver for "ti,sysc" compatible property in SPL
the buses marked with this compatible string must also be marked with
compatible = "simple-bus" to make the underlying devices visible in
SPL. Otherwise the matching device drivers aren't found and the uclass
drivers are dropped.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
The SPI and NAND board variants never went into production.
Drop those board variants.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
This is required for architectures which do not support compressed kernel images (i.e. ARM64). This is only used while not booting via FIT image.
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.
But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222 ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.
The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.
Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.
After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.
To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.
Fixes: 5bb2c550b1 ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
For some unknown reason when L2 cache is disabled on Armada 385 then loadb,
loadx and loady commands do not work with higher baudrates than 115200
(they just abort transfer) and lzmadec command with lzma image of size
0x7000000 (maybe even smaller, we tested this one) is doing decompression
for more than 2 minutes. After enabling L2 cache decompression takes only
30s and loadb, loadx and loady are stable and working fine.
git bisect identified problematic commit 3308933d2f ("arm: mvebu: Avoid
reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit
above issues were not present.
But investigation showed that above issue was possible to reproduce also by
reverting that commit and forcing compiler to do inline optimization of
mvebu_soc_family() function. Which seems that the root of this issue is in
caches and position of instruction of segments. So currently it is unknown
what is or was broken, but code movement, code inlining or other compiler
optimization triggered it.
Commit 3e5ce7ceeb ("arm: mvebu: Enable L2 cache on Armada XP") mentioned
that enabling L2 cache on Armada XP improved performance and that Armada
38x has L2 disabled (which is default state) and if needed it has to be
enabled in separate patch. As enabling L2 cache also improve performance
on Armada 38x, enable it.
Note that Aurora cache in no outer mode is available only on Armada XP,
hence it is not touched for Armada 38x code.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Reported-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Replace magic constant 1 when disabling MMU by macro CR_M from include
header file asm/system.h.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada
XP at all") introduced branch for non-AXP code which was guarded by A38X
condition. Fix this issue by checking for AXP platform, not by A38X.
Fixes: c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada XP at all")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID
register too many times") broke support for caches on all Armada SoCs.
Before that commit there was code:
if (mvebu_soc_family() != MVEBU_SOC_A375) {
dcache_enable();
}
And after that commit there is code:
if (IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Comment above this code says that d-cache should be disabled on Armada 375.
But new code inverted logic and broke Armada 375 and slowed down all other
Armada SoCs (including A38x).
Fix this issue by changing logic to:
if (!IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Which matches behavior prior that commit.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Move arm twd timer driver from zynq to generic location.
DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmMZoW4ACgkQ4rK92eCq
k3W2MAgAsmy2aSlMYo/AGlJ/KCrZuk6OirNHtdOdacvbcdUUbpkNpBSjdkrRm2If
VUnY1utIIJe6gFgnBUxXJ3RF5FZuhkdawc6V25HtDp6H3WamzJknKs5Vc4TlKp59
hZCOto7/+G/cd2XLdCKFUBl+new1pdDPsEm56+57DeZ7QGAQRX35PUQ5+HBjQJ/N
n/wJgS6wkEdIQLLwmCVxbHUkC+pRotTza5F2A0qZJgYPMcMpVFYKtzIa4GbWB5YS
MKGHbM8f3C8RLPQaHHTRycoA2Yor1I52B4Oi7605c5zHQr9pjrgtWsernDzkIhsB
ThYHSYQBUBTY4HBfzFwzCkVGqqLWNg==
=PMFY
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20220907' of https://source.denx.de/u-boot/custodians/u-boot-stm
- simplify the STM32MP15x package parsing code
- remove test on CONFIG_DM_REGULATOR in stm32mp1 board
and enable CONFIG_DM_REGULATOR for stm32f769-disco
- handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start'
after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>)
- Fix SYS_HZ_CLOCK value for stih410-b2260 board
- Switch STMM32MP15x DHSOM to FMC2 EBI driver
- Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel
This reduces sec_firmware_get_data to a single call to
fit_get_data_conf_prop. I think sec_firmware_check_copy_loadable could also
be converted, but it does not map as straightforwardly, so I have left it
for a future cleanup.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The config to use for FIT images can be better specified by enabling
CONFIG_MULTI_DTB_FIT and implementing board_fit_config_name_match.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Removes hwlocks properties from stm32mp151 pinctrl node. These locks
could be used for other purpose, depending on board and software
configuration hence do not enforce their use to protect pinctrl
devices.
This patch is an alignment with Linux device tree with v6.0 as the
hwsem support wasn’t yet added in pincontrol in kernel. It avoids
issues when the Linux kernel is started with the U-Boot device tree.
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Perform long overdue conversion of ad-hoc FMC2 EBI bus initialization
to upstream FMC2 EBI driver. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Since commit ef4ce6df32 "video: stm32: stm32_ltdc: fix data enable polarity"
The panel display output wasn't functional anymore.
Device tree display-timings de-active property value must be updated
to 1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Simplify the package parsing code for STM32MP15X as package can be
affected with get_cpu_package() result.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
By default the OCRAM is marked as secure. While the SPL runs in EL3 and
thus can access it, DMA devices cannot. Mark the whole OCRAM as
non-secure.
This will fix MMC and SD card boot on LS1028A when using SPL instead of
TF-A.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This new image is similar to u-boot-rockchip.bin except that it's
destined to be flashed on SPI-NOR flashes.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This prepares for the creation of a u-boot-rockchip-spi.bin image
similar to u-boot-rockchip.bin to the exception it's destined for
SPI-NOR flashes instead of MMC storage medium.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This allows to build u-boot-rockchip.bin binary with binman for Rockchip
ARM64 boards instead of the legacy Makefile way.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
idbloader.img content - currently created by way of Makefile - can be
created by binman directly.
So let's do that for Rockchip ARM platforms.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
While technically not a bug, let's have some consistency in paths
returned by u-boot,spl-boot-order look-up and the one saved in
u-boot,spl-boot-device by syncing spl_boot_devices_tbl and boot_devices
node paths.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On RK3399, mmc0 is eMMC and mmc1 is SD card, c.f. console:
MMC: mmc@fe320000: 1, mmc@fe330000: 0
In arch/arm/mach-rockchip/spl-boot-order.c:board_boot_order, the
boot_device (BOOT_DEVICE_*) value is gotten from spl_node_to_boot_device
function. Said function returns BOOT_DEVICE_MMC1 for mmc0 (eMMC) and
BOOT_DEVICE_MMC2 for mmc1 (SD card).
Since the SD card controller is at mmc@fe320000, it should be associated
with BOOT_DEVICE_MMC2 and not BOOT_DEVICE_MMC1. Same applies to eMMC.
Let's fix that by swapping the two BOOT_DEVICEs.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Rockchip SoCs need the boot_devices array defined in order to map the
bootloader's value to a U-Boot device. Implement this for rk3308.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When idbloader.img is flashed on the eMMC, the SPL still tries to load
from SPI-NOR first.
This is due to an incorrect look-up in the Device Tree. Since commit
822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux"), the
node name (but not label) changed from sdhci@fe330000 to mmc@fe330000
meaning U-Boot SPL is not looking for the correct node name anymore and
fails to find the "same-as-spl" node when eMMC is the medium from which
the SPL booted.
Fixes: 822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Artem Lapkin <email2tema@gmail.com>
Tested-by: Artem Lapkin <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The boot_devices constants for rk3288 were changed to match the
binding, but the dtsi file was not synced.
Fix by renaming the rk3288 mmc node names.
Also correct the clock name for "ciu-drive".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
LTO (Link-Time Optimisation) is an very useful feature which can
significantly reduce the size of U-Boot binaries. So far it has been
made available for selected ARM boards and sandbox.
However, incremental builds are much slower when LTO is used. For example,
an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7
seconds with LTO enabled.
Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be
disabled during development if needed, for faster builds.
Add some documentation about LTO while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).
A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.
v1 -> v2:
Comment update. Pointed out by Andre Przywara.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
The compatible values used for device nodes representing Renesas Reduced
Pin Count Interfaces were based on preliminary versions of the Device
Tree Bindings.
Correct them in both DTSi files and drivers, to match the final DT
Bindings.
Note that there are no DT bindings for RPC-IF on RZ/A1 yet, hence the
most logical SoC-specific value is used, without specifying a
family-specific value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to the Generic Names Recommendation in the Devicetree
Specification Release v0.3, and the DT Bindings for the Renesas Reduced
Pin Count Interface, the node name for a Renesas RPC-IF device should be
"spi". Especially on R-Car Gen3 and RZ/G2, the node name matters, as
the node is enabled by passing a DT fragment from TF-A to U-Boot, and
from U-Boot to subsequent software.
Fix this by renaming the device nodes from "rpc" to "spi".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the
SPL to build cache-pl310.c.
Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner <pro@denx.de>
This converts CONFIG_SYS_L2_PL310 to Kconfig.
For omap2 and mvebu the 'select SYS_L2_PL310' locations were
determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.
For mx6 I manually chose ARCH_MX6 as 'select' location. The
correctness has been verified using
$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF
0 matches
That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this
was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert
the 'select' statement under ARCH_MX6.
Signed-off-by: Philip Oberfichtner <pro@denx.de>
Newer versions of GCC won't initialize parts of structures which don't
appear to be used. This results in uninitialized semihosting parameters
passed via R1. Fix this by marking the inline assembly as clobbering
memory.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
