Commit graph

13 commits

Author SHA1 Message Date
Patrick Delaunay
c480138958 phy: stm32: usbphyc: manage optional vbus regulator on phy_power_on/off
This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:02:58 +01:00
Sean Anderson
0aeaca622a phy: usbphyc: Fix not calling dev_err with a device
Use the phy's device.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:36 -04:00
Patrick Delaunay
9f9191a107 phy: usbphyc: use regulator_set_enable_if_allowed for disabling vdd supply
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while disabling vdd supply. This way the driver doesn't see an error
when disabling an always-on regulator.

This patch is needed since the commit f93fab3126 ("Revert 'power:
regulator: Return success on attempt to disable an always-on regulator'")
and use the API introduced by commit cc4a224af2 ("power: regulator:
Introduce regulator_set_enable_if_allowed api").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:00:05 +02:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Patrick Delaunay
901f6950a4 phy: usbphyc: increase PLL wait timeout
wait 200us to solve USB init issue on device mode
(ums and stm32prog commands)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Patrick Delaunay
e1904abc1b phy: usbphyc: move vdda1v1 and vdda1v8 in phy_init
vdda1v1 and vdda1v8 are used by the PLL.
Both need to be enabled before starting the PLL.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Patrick Delaunay
c50151d43f phy: usbphyc: Binding update of vdda supply
Move supply vdda1v1 and vdda1v8 in usbphyc node and
no more in port

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Patrick Delaunay
1655f2da84 phy: usbphyc: update xlate with DT binding
Parameter added for port 1, for example:

&usbh_ehci {
	phys = <&usbphyc_port0>;
	phy-names = "usb";
	vbus-supply = <&vbus_sw>;
	status = "okay";
};

&usbotg_hs {
	pinctrl-names = "default";
	pinctrl-0 = <&usbotg_hs_pins_a>;
	phys = <&usbphyc_port1 0>;
	phy-names = "usb2-phy";
	status = "okay";
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Patrick Delaunay
6841d83cec phy: usbphyc: remove unused variable index
Remove unused field index in struct stm32_usbphyc_phy.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-21 10:26:51 +02:00
Tom Rini
624d2cae34 SPDX: Fixup SPDX tags in a few new files
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-20 09:47:45 -04:00
Patrice Chotard
3b29121678 phy: add support for STM32 usb phy controller
This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-18 13:17:31 +02:00