3 commits

Author	SHA1	Message	Date
Masahiro Yamada	c72f4d4c2e	ARM: uniphier: add PLL init code for LD11 SoC ... - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>	2016-09-23 01:00:23 +09:00
Masahiro Yamada	682e09ff9f	ARM: uniphier: add PLL init code for LD20 SoC ... Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>	2016-09-19 00:12:26 +09:00
Masahiro Yamada	650aedbfc0	ARM: uniphier: add System Control register macros for ARMv8 SoCs ... The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>	2016-03-24 01:45:22 +09:00