Commit graph

8 commits

Author SHA1 Message Date
Lokesh Vutla
ccd2f8db81 ARM: AM43xx: Fix UART clocks enabling
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-06-06 17:46:15 -04:00
Mugunthan V N
2cab8ae85d ARM: AM43xx: clocks: Enable CPGMAC clock control
Enable CPGMAC clock control for AM43xx to use ethernet in U-Boot

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-03-04 09:42:06 -05:00
Tom Rini
eeb72e6761 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	arch/arm/cpu/armv7/config.mk
	board/ti/am43xx/mux.c
	include/configs/am43xx_evm.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-26 16:49:58 -05:00
Dave Gerlach
cd8341b7eb ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
2014-02-21 13:55:40 -05:00
Sourav Poddar
b56e71e2d4 am43xx: Add qspi support
Add QSPI definitions and clock configuration support.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-02-18 22:41:08 +05:30
Lokesh Vutla
cf04d0326b ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
0d54cb924e ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
3b34ac13fe ARM: AM43xx: clocks: Add dpll and clock data
Add dpll and clock data for AM43xx

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-08-15 08:51:10 -04:00