This patch has been sent on:
- 29 Sep 2007
Although mips_io_port_base is currently a part of IDE command, it is quite
fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
it to MIPS general part, and introduce `set_io_port_base()' from Linux.
This patch is triggered by multiple definition of `mips_io_port_base' build
error on gth2 (and tb0229 also needs this fix.)
board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if
the most significant bit was set, which did not work on any
architecture where "char" defaulted to be an unsigned type.
Based on a patch by Angelos Manousaridis <amanous@inaccessnetworks.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds changes needed for Makalu rev 1.1:
- Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
- Enable 2nd ethernet port EMAC1
- Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
- Reset PCIe ports via GPIO upon bootup
Signed-off-by: Stefan Roese <sr@denx.de>
This change is in preparation for condtitionial compile support in the
build system. By spliting them all into seperate lines now, subsequent
patches that change 'COBJS-y += ' into 'COBJS-$(CONFIG_<blah>) += ' will
be less invasive and easier to review
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h
Signed-off-by: Stefan Roese <sr@denx.de>
This patch makes the sequoia board use the generic usb-ohci driver
instead of cpu/ppc4xx/usb_ohci.c.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch disables the 44x d-cache on 'usb start' and
reenables it on 'usb stop'. This should be seen as a
temporary fix until the generic usb-ohci driver can
life with d-cache enabled.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes some redundant code and decrements the end
address of cache flush and invalidate by 1.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".
This patch also has a little code cleanup integrated.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch implements general ULi 526x Ethernet driver.
Until now, it is the only native Ethernet port on
MPC8610HPCD board, but it could be used on other boards
with ULi 526x Ethernet port as well.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and
"miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which
returns non-zero iff the PHY registers are configured for 1000BASE-X. The
"mii info" command is modified to distinguish between 1000BASE-T and -X.
Signed-off-by: Larry Johnson <lrj@acm.org>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
