3 commits

Author	SHA1	Message	Date
Zong Li	662e300bc0	riscv: cpu: fu740: Fix typo of date ... Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2021-08-17 19:28:37 +08:00
Green Wan	c552debbd8	riscv: cpu: fu740: clear feature disable CSR ... Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>	2021-05-31 16:35:55 +08:00
Green Wan	a74e9d899d	riscv: cpu: fu740: Add support for cpu fu740 ... Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2021-05-31 16:35:53 +08:00