3 commits

Author	SHA1	Message	Date
Wheatley Travis	f5a2425919	7450 and 86xx L2 cache invalidate bug corrections ... The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com> Acked-By: Jon Loeliger <jdl@freescale.com>	2008-05-09 20:46:48 +02:00
Jon Loeliger	cccce5d058	Remove L2 Cache invalidate polling.	2006-05-19 13:54:02 -05:00
Jon Loeliger	debb7354d1	Initial support for MPC8641 HPCN board.	2006-04-26 17:58:56 -05:00