Commit graph

7 commits

Author SHA1 Message Date
Paul Burton
bea12b7823 malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.

Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-26 21:49:34 +01:00
Paul Burton
81f98bbd62 malta: setup PIIX4 interrupt route
Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will
be left disabled. Linux does not set up this routing but relies upon it
having been set up by the bootloader, reading back the IRQ lines which
the PIRQ[A:D] signals have been routed to.

This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11.
This matches the setup used by YAMON.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:02 +01:00
Paul Burton
3ced12a06b malta: enable RTC support
This is actually required in order for a Linux kernel to boot
successfully on a physical Malta board. Without enabling the RTC, a
Malta Linux kernel will get stuck in its estimate_frequencies function
on boot.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:02 +01:00
Paul Burton
e0ada6319b malta: display "U-boot" on the LCD screen
Displaying a message on the LCD screen is a simple yet effective way to
show the user that the board has booted successfully.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
baf37f06c5 malta: support for coreFPGA6 boards
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.

Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.

Tested on:
  - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
    with and without an L2 cache.
  - QEMU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
a257f6263b malta: setup super I/O UARTs
On a real Malta the Super I/O needs to be configured before we are able
to access the UARTs. This patch performs that configuration, setting up
the UARTs in the same way that YAMON would.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
7a9d109b00 qemu-malta: rename to just "malta"
This is in preparation for adapting this board to function correctly on
a physical MIPS Malta board. The board is moved into an "imgtec" vendor
directory at the same time in order to ready us for any other boards
supported by Imagination in the future.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Renamed from board/qemu-malta/qemu-malta.c (Browse further)