2 commits

Author	SHA1	Message	Date
Alexey Brodkin	17b0da8019	axs101: flush DMA buffer descriptors before DMA transactons starts ... CPU sets DMA buffer descriptors with data required for inetrnal DMA such as: * Ownership of BD * Buffer size * Pointer to data buffer in memory Then we need to make sure DMA engine of NAND controller gets proper data. For this we flush buffer rescriptor. Then we're ready for DMA transaction. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com>	2014-03-28 15:06:30 -04:00
Alexey Brodkin	a7069ddfa9	arc: add AXS101 board support ... AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>	2014-02-07 08:14:33 -05:00