Commit graph

14 commits

Author SHA1 Message Date
Luis Araneda
9896dc6558 ARM: dts: zynq: correct and improve the model property of dt files
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Michal Simek
051a8ad7bb arm: zynq: Sync up licenses with mainline kernel
Use different location for SPDX line. Also update dates for new mainline
DTS files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:49 +02:00
Michal Simek
534f7e0235 arm: zynq: Sync location of DT properties with Linux
This is trival change which only ensures the same location with Linux
kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:08 +01:00
Sai Pavan Boddu
5fad1ab3d0 arm: zynq: Add device-type property for zynq ethernet phy nodes
Mention device-type = "ethernet-phy", as qemu will need this in absence
of compatible.

Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:07 +01:00
Michal Simek
cc7978bef9 ARM: zynq: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property

This patch is fixing them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:38 +01:00
Michal Simek
a195ed3359 ARM: zynq: Fix usb phy node for Zybo
Compatible property should be the first.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:02 +02:00
Michal Simek
a95d54b490 ARM: zynq: Align spi and qspi node locations
Keep nodes alphabelitally sorted.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Nathan Rossi <nathan@nathanrossi.com>
2016-04-13 18:29:02 +02:00
Michal Simek
936bbc5d16 ARM: zynq: Fix bootargs in board dtsi
- Sync with Linux kernel
- Remove rootfs
- Remove earlyprintk

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Michal Simek
baec7df738 ARM: zynq: Add reset-gpio property for USB on Zybo
DTS syncup with Linux kernel.
Add missing reset-gpio property.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-22 16:37:50 +01:00
Nathan Rossi
7bbf825492 arm: zynq: Update ZYBO config options
Update the ZYBO device tree and enable config options that relate to the
added devices in the device tree.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek
8647219b5c ARM: zynq: Enable u-boot,dm-pre-reloc for sdhci
Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo.
And create aliases for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-18 13:15:57 +01:00
Simon Glass
035c6b271d arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Michal Simek
999667ca9c ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel
Syncup with the latest DT from the Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Peter Crosthwaite
9757b65bef arm: dts: zynq: Add digilent ZYBO board dts
It's a Zynq board similar in design to the currently supported ones.
512MB of RAM and UART1 is used.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-11-11 11:02:07 +01:00