2 commits

Author	SHA1	Message	Date
Aswath Govindraju	ff0becea71	phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE ... Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>	2022-02-08 11:00:03 -05:00
Jean-Jacques Hiblot	1a83f9931e	phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC ... Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com	2021-07-27 10:57:12 +05:30