The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.
Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.
We change now the things as following for having a working SPI instance
in DM:
- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.
- in release bus we just reset the modulctrl to the reset-value (spi-
slave)
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
commit 8480792287
("spi: omap3: Skip set_mode, set_speed from claim") did break SPI
support on my AM335x board.
The named commit:
- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.
- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Otherwise the frequency is zero and the clock divider cannot be setup by
'omap3_spi_set_speed' function.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
CS GPIO activation low/high is determinated by the device tree
so we don't need to take in accoung in cs_activate and cs_deactivate
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch replaced "return 0" with "return status" to fix the
incorrect return value error reported by the coverity.
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Change to use devfdt_get_addr_index() function to get fdt address.
Original code has compilation warning below:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’:
drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
plat->regbase = (void *)data[0];
^
drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
plat->ahbbase = (void *)data[2];
^
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix warning as below when compile in 64-bit.
warning: format '%u' expects argument of type
'unsigned int', but argument 6 has type 'size_t
{aka long unsigned int}
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
In
void *rx_addr = NULL;
rx_add = A;
the first assignment has no effect. Remove it.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For SPI_XFER_BEGIN | SPI_XFER_END the code sets data_out = NULL.
In the debug statement we should not dereference this value.
As we do not transfer any data the debug statement is not needed in this
case anyway.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In some situation, QSPI controller is already configured by an early
boot stage, adding reset support will insure that QSPI controller is
started from a pristine state.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Use dev_read_xxx() instead of old manner fdt_xxx() API
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add "st,stm32f469-qspi" compatible which is used on kernel side.
This will be necessary when DT will be synchronised from kernel.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
As all platforms which uses this driver have CONFIG_CLK flag
enable in their defconfig, we can remove it from driver code.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.
Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SPI
This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver. For now, just update
the CONFIG tests. This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.
Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Waiting for SPBDCR == 1 is not required and is covered by the
subsequent wait for SPSR_SPRFF, so drop this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Just replace unsigned {char,short,long} with u{8,16,32},
no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 7b09477873.
Signed-off-by: Tom Rini <trini@konsulko.com>
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 37434db29b.
Signed-off-by: Tom Rini <trini@konsulko.com>
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
ATMEL_SPI is now fully converted to driver-model and
respective boards switch to DM_SPI as well,
so make default y for ARCH_AT91
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
All board configs are now enabled DM_SPI for SPL and
U-Boot proper, so now its time to drop non-dm code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
struct udevice *bus = dev->parent;
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
