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3 commits

Author SHA1 Message Date
Chin Liang See
89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:07 +02:00
Marek Vasut
f6badb0d89 arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
ca62d2e1fc arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Renamed from board/altera/socfpga/wrap_sdram_config.c (Browse further)