hardware difference between leopard and orca as below:
flash setting leoaprd orca
bank size 32MB 64MB
bus width 32-bits 16-bits
Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
The timer3 counter unit for lastdesc and now values are inconsistent in current
code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is
second. However, CONFIG_SYS_HZ is defined as 1000 in board config file.
This means the accuracy of "lastdec" and "now" should be in millisecond,
thus fix the equation to set lastdec and now variables accordingly.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
The original adp-ag101/adp-ag101p initialize only one bank(64MB)
by default at boot time, but it is not enough for some application,
so increasing to two banks(128M).
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range
Signed-off-by: Macpaul Lin <macpaul@gmail.com>
SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.
This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
