A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.
- FAT write support (needed for SCT)
- improved FAT directory support (needed for SCT)
- RTC support with QEMU -M virt
- Sandbox support (run UEFI binaries in Linux - yay)
- Proper UTF-16 support
- EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
- EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
- Fix window size determination
- Fix Tegra by explicitly unmapping RAM
- Clean up handle entanglement
- Lots of generic code cleanup
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJbq6+cAAoJECszeR4D/txgV1cP+wZPVsY/kRDwCZ8PODOIyLW/
YWWX0CHOUNIXcvWyrQQVflRKE7IbsoPNU+PxOze/toBZvNGZofCqd/P0sT0kk8UU
/aQ55+Hn8/N4etysKxhk2uszBuEXZsOdprNV3H7tO9vKsMHpImAdLvIyviYK0eCF
WnNsmDVFv/W4M5IWDJrS7KqwTuLPYE5Xli9BW/O2qi8NOvpfyb4EEqdL7OHyHAxe
8zpzyaRXJkPcgPkJ6z3WZ+BmAuXSl5DsLWqfsnZJQzkXatRhT8PneRk787e+xK3A
OEFarj5t/94T1KivxquM9iYi0NzwGWrrCfRzbQh5klV4Z/bRYHbGQ92j6iZyfnpj
0zvWrJCalDaUz310BKZDyzKYQnoDj5/iYaMJHtaG6zmkXCzM41kniGKxuy/3IpTB
ozeFtH2AOwlAFZRIzQiazkyU0bizis2Y/K4xzOQczvVajdLW0DsLXL/hyqaFaGO2
3oVK350FXMHKa1UhpsG05aoQvyYq8N4YVEfOSdBKah8qhhMG8zZ2IaX5oheZJjr4
yPV8iaSj8trX3mI9clsnX9YT7qJdcS188JYSii+8SVpVH4VpgwvUSHfDqznn7JNz
COue6rFo9sg55Le9OsoxUgaQ5GO4oz+5iGmfyBmOtQ3n83JxmP4CJK84Ykw2i9fi
sxJR6aNtktsLhfYhlDO/
=ZuJG
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-09-26
A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.
- FAT write support (needed for SCT)
- improved FAT directory support (needed for SCT)
- RTC support with QEMU -M virt
- Sandbox support (run UEFI binaries in Linux - yay)
- Proper UTF-16 support
- EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
- EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
- Fix window size determination
- Fix Tegra by explicitly unmapping RAM
- Clean up handle entanglement
- Lots of generic code cleanup
[trini: Fixup merge conflict in include/configs/qemu-arm.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch moves the PM version related macros to .h file so that
they can be reused in other files.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make use of asm-generic/atomic.h retaining the smp_mb_... definitions.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The MMC card detect pin is connected to gpio127 on omap3_logic.
When setting up the pbias register for MMC, let's also enable
gpio_127 for the card detect. As part of the package deal,
gpio_126 and gpio_129 are also enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike
the current 0x70 which enables the clock of UART2, SSP1 and SSP2.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Stefan Roese <sr@denx.de>
SPI controllers SSP1, 2 and 3 require to enable their respective clocks.
Let's enable them only when the SPI controller driver is built.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Virtual machine provided by qemu-arm has a ARM PL031 Real Time Clock
device. With this patch, the driver is enabled by default.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tegra U-Boot ensures that board_get_usable_ram_top() never returns a value
over 4GB, since some peripherals can't access such addresses. However, on
systems with more than 2GB of RAM, RAM bank 1 does describe this extra
RAM, so that Linux (or whatever OS) can use it, subject to DMA
limitations. Since board_get_usable_ram_top() points at the top of RAM
bank 0, the memory locations describes by RAM bank 1 are not mapped by
U-Boot's MMU configuration, and so cannot be used for anything.
For some completely inexplicable reason, U-Boot's EFI support ignores the
value returned by board_get_usable_ram_top(), and EFI memory allocation
routines will return values above U-Boot's RAM top. This causes U-Boot to
crash when it accesses that RAM, since it isn't mapped by the MMU. One
use-case where this happens is TFTP download of a file on Jetson TX1
(p2371-2180).
This change explicitly tells the EFI code that this extra RAM should not
be used, thus avoiding the crash.
A previous attempt to make EFI honor board_get_usable_ram_top() was
rejected. So, this patch will need to be replicated for any board that
implements board_get_usable_ram_top().
Fixes: aa909462d0 ("efi_loader: efi_allocate_pages is too restrictive")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL
too. This simplifies the conditional.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
If PCIe Mox module is connected we want to have PCIe node enabled
in U-Boot's device tree.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Remove smi_pins definition since it is already in armada-37xx.dtsi.
Add assigned-clocks definitions to spi0.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
The bootROM in the Armada-38x (and similar) SoC has two modes for UART
boot. The first is when the normal boot media is blank (or otherwise
missing the kwb header). The second is when the boot sequence has been
interrupted with the magic byte sequence on the UART lines.
In the first mode the bootROM routine and error code register will
indicate that there was an error booting from the configured media in
bits 7:0. In the second mode there is no error to indicate but the boot
source is provided via bits 31:28.
Handle both situations so that kwboot can be used for both boot
strapping a blank board and for intercepting a regular boot sequence.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
This reverts commit e83e2b3900. This
prevents kwboot from overriding the hardware strapped boot source.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Detect the SD/eMMC boot device at run-time. Load the environment from
the boot deice, as well as save to it.
Leave the environment offset the same as in the SPI flash.
Make SD/eMMC 0 the default environment device when the boot device is
not detected.
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
just try to bring up an imx6ull board with console
on uart5 and found, that input_val for pin
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX is 7 and
not 5 on imx6ull.
With this patch rx works now.
Signed-off-by: Heiko Schocher <hs@denx.de>
There are two versions of imx6ul pico SOMs: one with 256MB and another
one with 512MB of RAM.
Convert to SPL so that both versions can be supported. This patch
doesn't rework the clock initialization to avoid changing the behavior
in this same patch, so it will be cleaned up in future.
Currently only the 256MB is tested/supported.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
With DM enabled, this patch enables DM_SERIAL and removes
the NS16550 initialization from da850_lowlevel since the driver
will take care of that itself.
Signed-off-by: Adam Ford <aford173@gmail.com>
boot-common.c checks to see if I2C is enabled in SPL, but
it doens't check for DM_I2C before initializing it. This
will now only initialize the I2C is the DM_I2C is not enabled
to avoid initializing it more than once.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the re-sync from Linux 4.18, several entries in
da850-evm-u-boot.dtsi are no longer necessary, so this patch
removes them.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add the minimum dt nodes required to boot. These nodes
will get deleted as kernel gets these nodes added in the
main dts files.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add initial support for AM654 based EVM running on A53. Enable
4GB of DDR available on the EVM so that kernel DTB file
can be updated accordingly.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[Andreas: Added 4GB ddr support]
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
As no gpio.h is defined in arch/arm/mach-k3/include/,
to avoid compilation failure, do not include asm/arch/gpio.h.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update Makefile to generate
- tispl.bin: First stage bootloader on ARMv8 core
- u-boot.img: Second stage bootloader on ARMv8 core.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
By default the device control module registers are locked,
preventing any writes to its registers.
Unlock those registers as part of the init flow.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM654 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and
expects to start executing from 0x0. In order to handle this ROM
updates the boot vector of R5 such that first 64 bytes of image load
address are mapped to 0x0.
In this case, it is SPL's responsibility to jump to the proper image
location. So, update the PC with address of reset vector(like how
other exception vectors are handled), instead of branching to reset.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM654 device is designed for industrial automation and PLC
controller class platforms among other applications. Introduce
base support for AM654 SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The MIO clock is enabled by default, and the STDMAC clock is
enabled by the clk driver. The ad-hoc way to enable the clock
is no longer needed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There are multiple GPIOs that can be used with the same driver depending
on the CONFIG_GPIO_BASE defined in the controller driver.
GPIO3 and 4 require a clock to be enabled so let's enable them when the
driver is built.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Add support for loading U-Boot on the Broadcom 7260 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Four different boards had different options for enabling cache
that were virtually all the same. This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c
This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit fixes various devicetree warnings in the at91 devicetrees
like:
arch/arm/dts/sama5d36ek_cmp.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
These warnings make buildman report failed builds for most of at91 boards.
Thus, fixing it.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
For at91family, makefile was building unwanted DTBs
Moved them under specific target configuration.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.
Factor out the duplicated code into <asm-generic/int-ll64.h>.
BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/Makefile references armv5 for backwards compatibility with
older compilers. This patch removes those references to armv5,
since by now newer compilers are required which should have armv7
support enabled.
The Makefile also also has a list of options for mtune, but the
entry for CONFIG_CPU_V7A is empty, so this patch tunes the
CPU_V7A architecture to generic-armv7-a.
The following size changed apply to omap3_logic using GCC.
Stock
text data bss dec hex filename
50910 429 67580 118919 1d087 spl/u-boot-spl
540713 22700 327072 890485 d9675 u-boot
Without Armv5
text data bss dec hex filename
50916 429 67580 118925 1d08d spl/u-boot-spl
540719 22700 327064 890483 d9673 u-boot
mtune=generic-armv7-a
text data bss dec hex filename
50932 429 67580 118941 1d09d spl/u-boot-spl
540519 22700 327080 890299 d95bb u-boot
Signed-off-by: Adam Ford <aford173@gmail.com>
In commit a1274cc94a ("ARM: Page align secure section only when it is
executed in situ"), we used output section attributes (the "ALIGN"
keyword after the colon) to specify the alignment requirements. Using
the constant "COMMONPAGE" there was recently broken in binutils 2.31 [1].
Binutils maintainer Alan Modra suggested the former method would still
work. Since both methods achieve the same result, this patch does just
that. This fixes the "reboot after bootm" issue we've been seeing on
sunxi when booting non-secure.
[1] https://sourceware.org/bugzilla/show_bug.cgi?id=23571
Suggested-by: Alan Modra <amodra@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Jagan Teki <jagan@openedev.com>
When re-syncing the DTS files from the kernel, something caused
the MMC driver to no longer detect the MMC card. Undoing the
CD-invert appears to fix the issue.
Fixes: e6ea2390cd ("ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit
with Linux 4.18-RC4")
Signed-off-by: Adam Ford <aford173@gmail.com>
This patch adds system suspend/resume support,
when linux kernel enters deep sleep mode, SoC will go
into below mode:
- CA7 platform goes into STOP mode;
- SoC goes into DSM mode;
- DDR goes into self-refresh mode;
- CPU0/SCU will be powered down.
When wake up event arrives:
- SoC DSM mdoe exits;
- CA7 platform exit STOP mode, SCU/CPU0 power up;
- Invalidate L1 cache;
- DDR exit self-refresh mode;
- Do secure monitor mode related initialization;
- Jump to linux kernel resume entry.
Belwo is the log of 1 iteration of system suspend/resume:
[ 338.824862] PM: suspend entry (deep)
[ 338.828853] PM: Syncing filesystems ... done.
[ 338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done.
[ 338.842939] OOM killer disabled.
[ 338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[ 338.869717] PM: suspend devices took 0.010 seconds
[ 338.877846] Disabling non-boot CPUs ...
[ 338.960301] Retrying again to check for CPU kill
[ 338.964953] CPU1 killed.
[ 338.968104] Enabling non-boot CPUs ...
[ 338.973598] CPU1 is up
[ 339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
[ 339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
[ 339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
[ 339.385065] PM: resume devices took 0.400 seconds
[ 339.389836] OOM killer enabled.
[ 339.392986] Restarting tasks ... done.
[ 339.398990] PM: suspend exit
The resume entry function has to initialize stack pointer before calling
C code, otherwise there will be an external abort occur, in additional,
invalidate L1 cache must be done in secure section as well, so this
patch also adds assembly code back and keep it as simple as possible.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Add i.MX7D GPC initialization for low power mode
support like system suspend/resume from linux kernel:
- Pending IOMUXC IRQ to workaround GPC state machine issue;
- Mask all GPC interrupts for M4/C0/C1;
- Configure SCU timing;
- Configure time slot ack;
- Configure C0/C1 power up/down timing;
- Configure wakeup source mechanism;
- Disable DSM/RBC related settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This patch improves cpu hotplug, previous cpu_off
implementation is NOT safe, a CPU can NOT power down
itself in runtime, it will cause system bus hang due
to pending transaction. So need to use other online
CPU to kill it when it is ready for killed.
Here use SRC parameter register and a magic number
of ~0 as handshake for killing a offline CPU,
when the online CPU checks the psci_affinity_info,
it will help kill the offline CPU according to
the magic number stored in SRC parameter register.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.
To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.
This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary
for converting to use u-boot DM driver.
Two -u-boot.dtsi are added to modify compatible string of SPI flash
device to "spi-flash".
Signed-off-by: Ye Li <ye.li@nxp.com>
On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.
Other changes to support the DM QSPI:
- Add QSPI node and alias spi0.
- Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
conflict
- Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
align with kernel and also present the conflict.
- Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
"spi-flash"
- Remove iomux settings of qspi in board codes which is not needed
for DM driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
To support DM QSPI driver:
- Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
to "spi-flash" and add "num-cs" property.
- Enable DM SPI and DM SPI FLASH configurations
- Remove iomux settings of qspi1 in board codes which is not needed
for DM driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
To support DM QSPI driver
- Add spi0 and spi1 alias for qspi1 and qspi2.
- Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
to "spi-flash" and add "num-cs" property.
- Enable DM SPI/QSPI relavent configurations
- Remove iomux settings of qspi2 in board codes which is not needed
for DM driver.
- Add sf default settings. So running "sf probe" can detect the flash
Signed-off-by: Ye Li <ye.li@nxp.com>
Fix warning below:
unnecessary #address-cells/#size-cells without "ranges" or child "reg"
property
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It is not preferred to put SUNXI-specific code in the common place.
Change it to 'imply' property of ARCH_SUNXI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In an earlier proposed patch, bcmstb.c implemented timer_read_counter,
but it was updated to implement get_ticks instead. This patch updates
the declaration in timer.h accordingly.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
The NAND reset is missing from DT, so the reset manager cannot unreset the NAND.
Add the missing DT reset entry.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
The UART clock frequency can be obtained from the clock framework by the
ns16550 driver, so drop this redundant DT node.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Flag timer clock as DM pre-reloc, so that a timer driver can be used and
it can extract information about it's clock rate using the clock framework.
This patch also moves some of the pre-reloc flags into the core dtsi file,
this is because the timer is not board specific, but rather is used on all
boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.
The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
According to mailbox spec, software should send urgent command with
urgent register instead of COUT location. This patch write urgent
command index to urgent register.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Code checking and setting EMAC use fpga is in
populate_sysmgr_fpgaintf_module(). So, call to sysmgr_pinmux_init()
instead of populate_sysmgr_pinmux().
In sysmgr_pinmux_init(), it will call to both populate_sysmgr_pinmux()
and populate_sysmgr_fpgaintf_module().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Update README.falcon to use "none" for compression property for
ramdisk image to avoid being uncompressed upon loading.
Signed-off-by: York Sun <york.sun@nxp.com>
A secure monitor that runs before U-Boot, and hence causes U-Boot to run
in non-secure world, must implement a few operations that U-Boot
otherwise implements when running in secure world. Fix U-Boot to skip
these operations when running in non-secure world. In particular:
- The secure monitor must provide the LP0 resume code and own LP0
configuration in order to maintain security, so must initialize all
the PMC scratch registers used by the boot ROM during LP0 resume.
Consequently, U-Boot should not attempt to clear those registers,
since the register accesses will fail or cause an error.
- The secure monitor owns system security, and so is responsible for
configuring security-related items such as the VPR.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Since commit f2faffecb0, tegra: Convert to use binman
the dm-pre-reloc properties are removed.
This leads U-Boot not to enable the display on paz00
This patch restore the dm-pre-reloc properties allowing
the bootloader to output to the display panel
v4: - Spell project name as appropriate
v3: - Fix few typos
v2: - Add more characters to commit hash
Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Also add device_find_global_by_ofnode() that also find a device based on
the OF node, but doesn't probe the device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
In the current H6 CPU memory space code, the SUNXI in the macro name of
the SID address base is wrongly spelled as SNUXI, which leads to SID
readout not working.
Fix this macro name.
Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This converts the following to Kconfig:
CONFIG_MII
CONFIG_DRIVER_TI_EMAC
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
2), set this to 8.
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable support for USB PHY on the R-Car Gen2. This allows for both
of the USB host ports to be used on such boards.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
