Commit graph

595 commits

Author SHA1 Message Date
Konstantin Porotchkin
1d45329ada fix: nand: pxa3xx: Remove hardcode values from the driver
Obtain NAND controller setup parameters from the device
tree instead of using hardcoded values.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-05-09 13:38:18 +02:00
Ladislav Michl
18cae43b62 mtd: nand: Consolidate nand spl loaders implementation
nand_spl_load_image implementation was copied over into three
different drivers and now with nand_spl_read_block used for
ubispl situation gets even worse. For now use least intrusive
solution and #include the same implementation to nand drivers.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:26 -04:00
Masahiro Yamada
90d6500c0f drivers: remove Blackfin specific drivers
These drivers have no user since commit ea3310e8aa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-04-18 10:29:14 -04:00
Wenyou Yang
0de077df38 mtd: nand: atmel: use another functions to set gpio value
Because there isn't the implementation of gpio_set/get_value()
and gpio_set/get_value() after the at91 gpio driver is converted
to support the driver model, use at91_set_gpio_value() and
at91_get_gpio_value()

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:49 -06:00
Cooper Jr., Franklin
6e1eb089be mtd: nand: am335x_spl_bch: Incorporate tWB delay in nand_command function
Various commands to NAND flash results in the NAND flash becoming busy.
For those commands the SoC should wait until the NAND indicates it is
no longer busy before sending further commands. However, there is a delay
between the time the SoC sends its last command and when the NAND flash
sets its Ready/Busy Pin. This delay (tWB) must be respected or the SoC may
falsely assume the flash is ready when in reality it just hasn't had enough
time to indicate that it is busy.

Properly delaying by tWB is already done for nand_command/nand_command_lp
in nand_base.c including the version of it in the Linux kernel. Therefore,
this patch brings the handling of tWB delay inline to nand_base.c

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[trini: Reformat comments slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-08 21:34:50 -04:00
Maxime Ripard
ff93c28265 nand: sunxi: Add options for the SPL NAND configuration
The SPL image needs to be built with a different ECC configuration than the
U-Boot binary.

Add Kconfig options with defaults to provide a value that should work for
anyone, but is still configurable if needs be.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:46 +05:30
Maxime Ripard
adc706b2fe mtd: sunxi: Change U-Boot offset
The default U-Boot offset for the Allwinner SoCs was set to 32kB.

This was probably to try to maintain some compatibility with the current
image that we build for the MMC where the U-Boot binary is also located at
a 32kB offset.

However, this causes a number of issues. The first one is that it prevents
us from using a backup SPL entirely, which is troublesome in case where the
first would be corrupt (especially on MLC which have a higher number of
bitflips).

We also cannot use the original MMC image on the NAND, because we need to
prepare the SPL image to include the ECCs and randomizer settings, which
reduces the interest of setting it at that particular offset.

It also prevents us from upgrading and flashing the U-Boot and SPLs
independantly, since it's very likely that it will fall in the same erase
block.

Since that default wasn't used by any board, change it for 8MB, which will
be in an erase block of its own, all the erase blocks being multiple of
two. The highest erase block size we encountered is 4MB, which means that
in this particular setup, the first and second erase blocks will be for the
SPL and its backup, and the third for U-Boot.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:46 +05:30
Maxime Ripard
5fe4c9f4d2 mtd: sunxi: Select the U-Boot location config option
We'll need that symbol so that the default offset are defined

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:45 +05:30
Maxime Ripard
ea3f750c73 nand: sunxi: Fix modulo by zero error
When trying to autodetect the ECC and randomization configurations, the
driver starts with a randomization disabled and no seeds.

In this case, the number of seeds is obviously 0, and the randomize boolean
is set to false.

However, the logic that retrieves the seed for a given page offset will
blindly use the number of seeds, without testing if the randomization is
enabled, basically doing a modulo by 0.

As it turns out, the libgcc in the common toolchain returns 0 here, which
was our expected value in such a case, and why we would not detect it.
However, U-Boot's libgcc will for some reason return from the function
instead, resulting in an error to load the U-Boot binary in the SPL.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07 11:23:45 +05:30
Tom Rini
ea3310e8aa Blackfin: Remove
The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05 13:52:01 -04:00
Hou Zhiqiang
203db38a94 mtd: nand: remove nand size print from nand_init function
Add nand_size() function to move the nand size print into initr_nand().
Remove nand size print from nand_init() to allow other function to call
nand_init() without printing nand size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:39:33 -07:00
Hou Zhiqiang
d72158c045 mtd: nand: add initialization flag
Add initialization flag to avoid initializing NAND Flash multiple
times, otherwise it will calculate a wrong total size.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 10:38:37 -07:00
Andrey Yurovsky
f78038dc0d mtd: nand: build MXS driver for MX7 as well
The i.MX7 has the same GPMI controller as i.MX6 and is covered by the MXS
driver. Tell Kconfig that we can use this driver on the MX7 platform (the MXS
driver already has the few i.MX7-specific changes needed for basic operation
and the board itself sets the pinmux correctly).

Tested on i.MX7D with the Sabre board and a NAND Flash soldered to U12.

Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
2017-02-19 16:20:28 +01:00
Ladislav Michl
6fe7fe12cc omap-gpmc: use SECTOR_BYTES instead of hardcoded value
Replace hardcoded value with defined constant SECTOR_BYTES.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-14 16:47:18 -05:00
Jagan Teki
101000b771 mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print
SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.

Original behaviour:
-------------------
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB

After the fix:
-------------
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB

Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:56:44 +01:00
Fabien Parent
cf07d39fb1 NAND: davinci: add support for NAND chips with 16 bits bus
The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add
support into the davinci driver for 16 bit bus NAND chips.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-03 13:21:15 -05:00
Boris Brezillon
11777a5ea7 mtd: nand: add support for the TC58NVG2S0H chip
Add the description of the Toshiba TC58NVG2S0H SLC nand to the nand_ids
table so we can use the NAND ECC infos and the ONFI timings.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-11-28 15:10:30 -05:00
Siva Durga Prasad Paladugu
02bcff2c56 nand: arasan_nfc: Clear ecc on bit while sending read command
Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:27:57 +01:00
Siva Durga Prasad Paladugu
ae798d2e7d mtd: nand: zynq_nand: Add nand driver support for zynq
Add nand flash controller driver support for zynq SoC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:27:50 +01:00
Jagan Teki
df10a850c5 mtd: nand: Kconfig: Add NAND_MXS entry
Added kconfig for NAND_MXS driver.

Cc: Scott Wood <oss@buserror.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26 16:53:16 +02:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Tom Rini
16f416661e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-09-09 09:45:32 -04:00
Stefan Agner
2a83c95fdb mtd: nand: mxs: fix cache alignment for cache lines >32
Currently the command buffer gets allocated with a size of 32 bytes.
This causes warning messages on systems with cache lines bigger than
32 bytes:
CACHE: Misaligned operation at range [9df17a00, 9df17a20]

Define command buffer to be at least 32 bytes, but more if cache
line is bigger.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06 18:22:48 +02:00
Scott Wood
8b7d51249e nand: Fix some more NULL name tests
Now that nand_info[] is an array of pointers we need to test the
pointer itself rather than using name as a proxy for NULLness.

Fixes: b616d9b0a7 ("nand: Embed mtd_info in struct nand_chip")
Signed-off-by: Scott Wood <oss@buserror.net>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2016-09-01 20:08:48 -05:00
Chris Packham
91395b5d4e mtd: nand: pxa3xx: use nand_set_controller_data
In commit 17cb4b8f32 ("mtd: nand: Add+use mtd_to/from_nand and
nand_get/set_controller_data") the assignment of mtd->priv was removed
but was not replaced. This adds the required nand_set_controller_data()
call.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2016-09-01 17:30:11 -05:00
Hector Palacios
ebb7febc92 mtd: nand: fix bug writing 1 byte less than page size
nand_do_write_ops() determines if it is writing a partial page with the
formula:
	part_pagewr = (column || writelen < (mtd->writesize - 1))

When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write, although
it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating until the watchdog timeout triggers.

To reproduce the issue on a NAND with 2K page (0x800):
	=> nand erase.part <partition>
	=> nand write $loadaddr <partition> 7ff

Signed-off-by: Hector Palacios <hector.palacios@digi.com>
2016-07-24 20:36:29 -05:00
Boris Brezillon
cd7f5e1cdf mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NAND
Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Boris Brezillon
4ccae81cda mtd: nand: Add the sunxi NAND controller driver
We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.

The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Brian Norris
42bd19ce6c mtd: nand: add common DT init code
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.

If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().

The original commit has been slightly reworked to use the fdtdec_xxx()
helpers (instead of the of_xxxx() ones).

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-07-24 20:36:28 -05:00
Ladislav Michl
0568dd0663 armv7: make gpmc_cfg const
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom Rini <trini@konsulko.com>

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-22 14:46:00 -04:00
Thomas Gleixner
e1a89e9358 nand_spl_simple: Add a simple NAND read function
To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-22 09:52:59 -04:00
Sumit Garg
8f01397ba7 powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:23 -07:00
Robert P. J. Day
62a3b7dd08 Various, unrelated tree-wide typo fixes.
Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-07-16 09:43:12 -04:00
Andre Renaud
62f8183f6a mtd: nand: Drop a blank line in nand_wait()
This empty line should not be there. Remove it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-06-24 17:23:14 -04:00
Tom Rini
2313d48445 Merge git://git.denx.de/u-boot-nand-flash 2016-06-20 05:15:52 -04:00
Boris Brezillon
30780f9483 mtd: nand: Patch remaining places where nand_to_mtd() should be used
Some drivers are still directly accessing the chip->mtd field. Patch
them to use nand_to_mtd() instead.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-06-19 19:28:38 -05:00
Max Krummenacher
e1c29086d5 nand: nand torture: follow sync with linux v4.6
follow parameter name change (nand to mtd) to fix compiler error.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2016-06-19 19:19:30 -05:00
Boris Brezillon
7748b41482 spl: nand: sunxi: add support for NAND config auto-detection
NAND chips are supposed to expose their capabilities through advanced
mechanisms like READID, ONFI or JEDEC parameter tables. While those
methods are appropriate for the bootloader itself, it's way to
complicated and takes too much space to fit in the SPL.

Replace those mechanisms by a dumb 'trial and error' mechanism.

With this new approach we can get rid of the fixed config list that was
used in the sunxi NAND SPL driver.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:02 -05:00
Boris Brezillon
4e7d1b3beb spl: nand: sunxi: split 'load page' and 'read page' logic
Split the 'load page' and 'read page' logic in 2 different functions so
we can later load the page and test different ECC configs without the
penalty of reloading the same page in the NAND cache.

We also move common setup to a dedicated function (nand_apply_config()) to
avoid rewriting the same values in NFC registers each time we read a page.

These new functions are passed a pointer to an nfc_config struct to limit
the number of parameters.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:01 -05:00
Boris Brezillon
bb9783b66b spl: nand: sunxi: rework status polling loop
check_value_xxx() helpers are using a 1ms delay between each test, which
can be quite long for some operations (like a page read on an SLC NAND).
Since we don't have anything to do but to poll this register, reduce the
delay between each test to 1us.

While we're at it, rename the max_number_of_retries parameters and the
MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that
we're actually waiting a given amount of time and not only a number of
retries.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:12:01 -05:00
Boris Brezillon
fa30115878 spl: nand: sunxi: stop guessing the redundant u-boot offset
Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess
where the redundant u-boot image is based on simple (and most of the time
erroneous) heuristics.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

# Conflicts:
#	drivers/mtd/nand/sunxi_nand_spl.c
2016-06-19 19:12:01 -05:00
Boris Brezillon
80ef700f8d spl: nand: support redundant u-boot image
On modern NAND it's more than recommended to have a backup copy of the
u-boot binary to recover from corruption: bitflips are quite common on
MLC NANDs, and the read-disturbance will corrupt your u-boot partitition
more quickly than what you would see on an SLC NAND.

Add an extra Kconfig option to specify the offset of the redundant u-boot
image.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
[scottwood: added ifdef to fix build break]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-19 19:11:57 -05:00
Boris Brezillon
494e108651 spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependency
The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced
to explicitly depend on platforms that are not already defining it in their
include/configs/<board>.h header.

Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS
depends on it, remove the dependency on NAND_SUNXI and make it dependent
on SPL selection.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 19:11:48 -05:00
Boris Brezillon
c4adf9db5d spl: nand: sunxi: remove support for so-called 'syndrome' mode
The sunxi SPL NAND controller driver supports use 'BootROM'-like configs,
that is, configs where the ECC bytes and real data are interleaved in the
page instead of putting ECC bytes in the OOB area.

Doing that has several drawbacks:
- since you're interleaving data and ECC bytes you can't use the whole page
  otherwise you might override the bad block marker with non-FF bytes.
- to solve the bad block marker problem, the ROM code supports partially
  using the page, but this introduces a huge penalty both in term of read
  speed and NAND memory usage. While this is fine for rather small
  binaries(like the SPL one which is at maximum 24KB large), it becomes
  non-negligible for the bootloader image (several hundred of KB).
- auto-detection of the page size is not reliable (this is in my opinion
  the biggest problem). If you get the page size wrong, you'll end up
  reading data at a different offset than what was specified by the caller
  and the reading may succeed (if valid data were written at this address).

For all those reasons I think it's wiser to completely remove support for
'syndrome' configs. If we ever need to support it again, then I'd recommend
specifying all the config parameters through Kconfig options.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2016-06-19 18:52:35 -05:00
Tom Rini
fd9102dafe Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-06-13 08:50:58 -04:00
Andre Renaud
65319f15ca at91: nand: Set up the ECC strength correctly
This needs to be set to avoid a fatal error when ECC is used.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12 23:49:38 +02:00
Andre Renaud
5a9ae33316 at91: Correct NAND ECC register access
This uses the wrote base register value. Fix it.

Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12 23:49:38 +02:00
Tom Rini
3fc304b8d7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-06-12 12:51:34 -04:00
Heiko Schocher
3a504d9639 mtd: nand: omap: allow to switch to BCH16
support in omap_nand_switch_ecc() also an eccstrength
from 16.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09 13:53:12 -04:00
Heiko Schocher
5d29e27eb9 nand: add nand mtd concat support
add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09 13:53:12 -04:00