The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.
Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.
Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.
Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).
Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.
Signed-off-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.
After the autocalibration issue is fixed we will enable it again.
Signed-off-by: Stefan Roese <sr@denx.de>
Some Blackfin UARTs are read-to-clear while others are write-to-clear.
This can cause problems when we poll the LSR and then later try and handle
any errors detected.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The USB/LAN register settings are not actually used/needed in order to
drive things from U-Boot, so drop the code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make sure that the start.o object is always the first object in our linker
script regardless of configuration settings, and add some linker symbols
so the ldr utility can properly locate the initcode when generating a LDR.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Use the sti instruction to set the initial interrupt mask rather than
banging on the core IMASK MMR to save both space and time.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We should use the algorithm in the Linux kernel so that the UART divisor
calculation is more accurate. It also fixes problems on some picky UARTs
that have sampling anomalies.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
During cpu init, make sure we initialize the CEC properly so that
interrupts can fire and be handled while U-Boot is running.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If booting out of NAND, we need to make sure we initialize it properly
before attempting to relocate the environment.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With this patch u-boot can fixup the dr_mode and phy_type properties
for the Dual-Role USB controller.
While at it, also remove #ifdefs around includes, they are not needed.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.
This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.
The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3, you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.
Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:
- When the CPLD recognizes its location on the PIB it automatically
configures RCW to the PCI Host.
- If the CPLD fails to recognize its location then it is automatically
configured as an Agent and the PCI is configured to an external arbiter.
This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
any arbiter bad things will happen (here the board hangs during any config
space reads).
In this situation we must disable the PCI. And in case of anybody really
want to use an external arbiter, we provide "pci_external_aribter"
environment variable.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This involves configuring the SerDes and fixing up the flags and
PHY addresses for the TSECs.
For Linux we also fix up the device tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
We'll use these masks to parse TSEC modes out of HRCWH.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).
Though, for SGMII we'll need 125MHz clocks.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC837xE specs says that SerDes1 has:
— Two lanes running x1 SGMII at 1.25 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.
And for SerDes2:
— Two lanes running x1 PCI Express at 2.5 Gbps;
— One lane running x2 PCI Express at 2.5 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.
The spec also explicitly states that PEX options are not valid for
the SD1.
Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
which is wrong to do.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).
This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).
With this patch we're able to:
- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
sparse/discontinuous memory model in the software.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
On some systems (for example Fedora Core 4) U-Boot builds with the
following wanrings only:
...
In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
from fdt.c:51:
/usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!
This patch fixes this problem.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: Stefan Roese <sr@denx.de>
I reorganized my config files, putting the common stuff into netstal-common.h
(got the idea by looking a amcc-common.h from Stefan).
Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's. Default behavior
is the existing single CPU print output. Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
