Commit graph

20 commits

Author SHA1 Message Date
Simon Glass
3c2d75269c rockchip: Drop SPL GPIO support for rk3288
This is not currently used and saves a little over 1KB of SPL image size.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-27 10:23:08 -06:00
Tom Rini
89cb2b5f8b configs: Re-sync with cmd/Kconfig
Update the config.h and defconfig files for the commands that 8e3c036
converted over to Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:47 -04:00
Tom Rini
cb04db155f include/configs: Whitespace fixup
A number of moveconfig.py runs have left a instances of multiple empty
lines in a row.  Correct this to a single empty line.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:46 -04:00
Tom Rini
78d1e1d0a1 configs: Re-sync almost all of cmd/Kconfig
This syncs up the current cmd/Kconfig and include/configs/ files with the
only exception being CMD_NAND.  Due to how we have used this historically
we need to take further care here when converting.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:40 -04:00
Simon Glass
69e173eb57 Move CONFIG_OF_LIBFDT to Kconfig
Move this option to Kconfig and tidy up existing boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 14:50:25 -04:00
Albert ARIBAUD
3709844f23 armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Simon Glass
30fc0fdded rockchip: config: Enable the 'gpio' command
Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
ad443b7290 rockchip: Don't skip low-level init
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
27a1961d0b rockchip: jerry: Enable the Chrome OS EC
Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
79d020ee74 rockchip: Use pwrseq for MMC start-up on jerry
This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Ariel D'Alessandro
cd3187d6b2 rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip Kconfig
Commit 1eb0c03c21 added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.

Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.

This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.

Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
302d1767b9 rockchip: add config decide whether to build common.c
some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
huang lin
cc2244b8fa rockchip: add timer driver
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Sjoerd Simons
abe919ec54 rockchip: firefly: Save the environment on SD card
Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Sjoerd Simons
9550e799e5 rockchip: Also load the initrd below 512M
Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Bin Meng
68d5342017 sf: Move SPI flash drivers to defconfig
There are already Kconfig options for SPI flash drivers, but we
have not moved them from config.h to defconfig files. This commit
does this in a batch.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-25 10:06:05 -05:00
Thomas Chou
9e39003e7f ns16550: move CONFIG_SYS_NS16550 to Kconfig
Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-21 21:50:18 -05:00
Masahiro Yamada
09f3ca3dd5 arm, powerpc: select SYS_GENERIC_BOARD
We have finished Generic Board conversion for ARM and PowerPC, i.e.
all the boards have been converted except OpenRISC, SuperH, SPARC,
which have not supported Generic Board framework yet.

Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro
defines in include/configs/*.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-24 13:50:38 -04:00
Sjoerd Simons
6460fc42a1 rockchip: Add config_distro_bootcmd support
Now that MMC works in U-Boot add config distro command support to start
Linux in a standard fashion. One oddity here is that linux fails to load
when the fdt is relocated to above 512MB, so set fdt_high to make sure it's
loaded below that.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:25 -06:00
Simon Glass
17aa548ced rockchip: Add basic support for firefly-rk3288
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00