Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Flexible static memory controller is a peripheral provided by ST,
which controls the access to NAND chips along with many other
memory device chips eg NOR, SRAM.
This patch adds the driver support for FSMC controller interfacing
with NAND memory.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the kmnusa build, this results in a corrupted important
env variable (bootcmd) but it may be that some other parts of the u-boot
binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to
board_init, which should be early enough in the boot sequence. The only
calls that could not be moved is the one for the SOFT (bitbang) I2C, and
they have been replaced by a direct access to the GPIO dataout Control
register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.
When the FPGA is not reconfigured, we only reset the PCIe part.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
In order to be able to perform board resets without interrupting the
traffic, the configuration of an already properly configured FPGA is
skipped.
This is because some PCIe FPGAs embed some other function that must
continue to work over reset.
It is then the responsibility of the application to trigger a
reconfiguration when needed. This is done by lowering the FPGA_INIT_B
pin for delaying the configuration to u-boot @ next reboot, and then
lower the FPGA_PROGRAM_B signal.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Some very similar #defines for reg addresses are used in a later patch
(managed_switch support for km_arm).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
the CPU can update the FPGA configuration when the kernel is running
The boards with a PCIe FPGA but without BOCO2 still are supported.
The config option name is CONFIG_KM_FPGA_CONFIG
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Use the generic header km_kirkwood.h and get rid of the
board specific header.
changes for v2: rebased because of changes in other patches
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy
between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Tom Rini <trini@ti.com>
The current configuration selects an incorrect NAND ECC layout,
which causes u-boot to write HW ECC data incorrectly.
This patch selects the right layout.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Currently on OMAP4/5 platforms, many kernel drivers are dependent
upon the bootloaders for mux, dpll and clock configurations.
This should not be the case and bootloaders should set only the
minimum required for the uboot functionality and kernel boot.
Note that this is going to break the kernel drivers. But this
is the only way to get things fixed in the kernel.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
USB module pads are getting enabled under non-essential
group. These will be required for fastboot, tftp support.
So move this to essential list to have them working when
non-essential pads are no more muxed.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
USB clocks will be required for fastboot, tftp
related functionalities. Move these clocks to
essential group inorder to have the functionality
working when non-essential clocks are not enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
GPMC clocks are currently getting enabled as a part
non-essential clocks. This will be required during
NOR boot. Move this to essential group to keep the
functionality, when non-essential clocks are not
enabled.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The external phy is present in the case OMAP5 soc is currently
configured in emif-common.c. This results in having dummy structures
for those Socs which do not have a external phy. So by having a weak
function in emif-common and overriding it in OMAP5, avoids the use
of dummy structures.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
This reduced M,N couple corresponds to the advised value from
TI HW team.
Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.
Signed-off-by: Sebastien Jan <s-jan@ti.com>
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
initialization takes more time and sometimes tftp fails
in RMII mode.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
The PLL setup values currently assume a 24 Mhz input clock.
This patch uses V_OSCK from the board config file to support boards
with different input clock rates.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so
Micron memory will not be detected!
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Some rams (Micron for example) return duplicate mr data on all byte lanes.
Users of the get_mr function currently don't deal with this duplicated
data gracefully. This patch detects the duplicated data and returns only
the expected 8 bit mr data.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Errata ID:i727
Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.
Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.
This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.
This will be used to skip the module configurations
that are retained across a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
We overwrite these weak functions from the kirkwood spi code to
use our own method to be able to switch between the SPI NOR and
the NAND flash. This is needed e.g. to update the u-boot. The former
command do_spi_toggle can therefore be removed. And the usage of
this command is removed from the u-boot update command in the
u-boot environment.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always
returns 8 for the PHY address. It is the reset value for the PHY
Address Register. Obviously, this default value could be incorrect.
Moreover, as the PHY address is well known, there is no need to
auto-detect it.
Now, the PHY address must given as a parameter to the PHY initialization
function. Additionally this patch also fixes some aesthetic issues.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch adds support for both the Linkstation Live (LS-CHLv2) and
Linkstation Pro (LS-XHL) by Buffalo.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Add new function eth_random_enetaddr() to generate a locally administered
ethernet address.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
Replace rand() with the functions from lib/. The link-local network code
stores its own seed, derived from the MAC address. Thus making it
independent from calls to srand() in other modules.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The kwboot program boots boards based on Marvell's Kirkwood platform
via Xmodem over their integrated UART.
Signed-off-by: Daniel Stodden <daniel.stodden@googlemail.com>
Acked-by: Luka Perkov <uboot@lukaperkov.net>
Tested-By: Holger Brunck <holger.brunck@keymile.com>
Tested-By: David Purdy <david.c.purdy@gmail.com>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
This allows a final, board specific, step in the claim/relase_bus
function for the SPI controller, which may be needed for some hardware
designs.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.
Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This was not done before, and in the case of a shared pin (for MPP0
between NF_IO[2] and CSn) this could lead to problems.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
With the new second save argument introduced by the previous patch, all
the calls to the function had to be fixed.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.
A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
We used to have an arbitrary value, which can be a problem if we have a
u-boot image that is bigger than this value.
This patch is dependant on the whole km/arm series and will be included
in the v3 of the series if there is one.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This is already defined in the generic kirkwood header.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
