Commit graph

187 commits

Author SHA1 Message Date
York Sun
fdb9f349be lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
2015-08-06 07:31:13 -06:00
Bin Meng
ae0518200f pci: Remove DEBUG from pci_compat.c
Remove DEBUG in drivers/pci/pci_compat.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 10:49:32 -06:00
Simon Glass
4bad2e7374 pci: Indicate prefetchable memory allocate when debugging
At present the PCI output displays 'Mem' when it allocates memory for a PCI
device, whether it is prefetchable or not. There is a distinction since the
memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating
prefetchable memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
5f48d798eb pci: Add a constant for an invalid interrupt
Rather than using 0xff in the code, add a constant.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
53292ad956 pci: Fix up code for CONFIG_PCI_ENUM_ONLY
This option is not used by any board but appears to still be useful, at least
for testing. With recent commits it does not build, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Simon Glass
da4b159bf0 pci: Use debug() instead of DEBUGF() in pci_auto.c
This file does not need its own way of doing debug(). Clean it up to use the
new way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:41 -06:00
Bin Meng
1e7a047304 x86: Sanity test on vesa parameters before setting up kernel screen_info
We should not set up kernel screen_info when the vesa parameters are
insane, otherwise kernel will panic.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Bin Meng
df189d9ba3 dm: pci: Allow scan bridge child devices before relocation
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. Remove such
limitation so that dm pci can be used before relocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:38 -06:00
Minghuan Lian
01cafcedbf drivers/pci/layerscape: Add EP mode support
The patch will initialize PCIe controller on EP mode
1. Setup bar:
   bar0 32bit 4K for specific configuration
   bar1 32bit 8K for MSIX
   bar2 64bit 4K for descriptor of memory
   bar4 64bit 1M for DMA memory test
2. Setup iATU:
   iATU inbound 0-3 to map bar transaction to memory address
   started at CONFIG_SYS_PCI_EP_MEMORY_BASE
   iATU outbound 0 to map 4G memory space

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
Minghuan Lian
ed5b580b38 drivers/pci: Add function to find an extended capability
PCIe extends device's configuration space to 4k and provides
extended capability. The patch adds function to find them.
The code is ported from Linux PCIe driver.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
Bin Meng
d11d9ef157 dm: pci: Support bridge device configuration correctly
Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.

The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.

For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.

To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:24 -06:00
Bin Meng
8326f136da dm: pci: Pass only device/function to pci_bus_find_devfn()
In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
4d8615cbf5 dm: pci: Use complete bdf in all pci config read/write routines
Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.

To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Bin Meng
95f3aa209a dm: pci: Correct primary/secondary/subordinate bus number assignment
In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28 10:36:23 -06:00
Simon Glass
4b515e4fc5 dm: pci: Add a function to get the BDF for a device
It is useful to be able to find the full PCI address (bus, device and
function) for a PCI device. Add a function to provide this.

Adjust the existing code to use this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:39 -06:00
Simon Glass
aba9296249 dm: pci: Add support for PCI driver matching
At present all PCI devices must be present in the device tree in order to
be used. Many or most PCI devices don't require any configuration other than
that which is done automatically by U-Boot. It is inefficent to add a node
with nothing but a compatible string in order to get a device working.

Add a mechanism whereby PCI drivers can be declared along with the device
parameters they support (vendor/device/class). When no suitable driver is
found in the device tree the list of such devices is consulted to determine
the correct driver. If this also fails, then a generic driver is used as
before.

The mechanism used is very similar to that provided by Linux and the header
file defintions are copied from Linux 4.1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-07-21 17:39:38 -06:00
Stuart Yoder
70e52d2115 armv8/fsl-lsch3: device tree fixups for PCI stream IDs
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Bin Meng
f110da9984 pci: Disable expansion ROM address decoding when signature check fails
We should not leave the expansion ROM address window open when there
is not a valid ROM.

Suggested-by: Matt Porter <mporter@konsulko.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:20 -06:00
Bin Meng
6c89663cb1 pci: Configure expansion ROM during auto config process
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:20 -06:00
Simon Glass
b9da5086b8 dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Simon Glass
945cae79e1 x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Bin Meng
a452002259 x86: Configure VESA parameters before loading Linux kernel
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-07-14 18:03:19 -06:00
Bin Meng
786a08e0dd x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Jian Luo
0e98a1473a video: Add 32-bit color depth support for VBE
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.

Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:18 -06:00
Simon Glass
5afeb4bb45 dm: pci: Correct bus number when scanning sub-buses
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Simon Glass
aec241dfb4 dm: pci: Use the correct hose when configuring devices
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.

This corrects a failure to scan and configure devices when driver model is
enabled for PCI.

Also add a comment to explain the problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:17 -06:00
Tom Rini
4d80051b63 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-06-08 08:37:02 -04:00
Tom Rini
d85cd29133 Merge git://git.denx.de/u-boot-dm 2015-06-05 11:21:08 -04:00
Simon Glass
2bb02e4fe2 dm: pci: Allow PCI bus numbering aliases
Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed
the default uclass behaviour to not support bus numbering. This is incorrect
for PCI and that commit should have enabled the flag for PCI.

Enable it so that PCI buses can be found and the 'pci' command works again.
Also add a test for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:34:47 -06:00
Bin Meng
04e3c4eb93 pci: Do not skip legacy IDE device configuration
The legacy IDE device has a BAR4 (Bus Master Interface BAR) which
needs to be configured.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
1b73b1c7fb pci: Allow debug message output in pci_auto.c
Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug
message output via '-DDEBUG'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
238fe16c40 pci: Move pci_hose_phys_to_bus() to pci_common.c
pci_hose_phys_to_bus() is needed by several drivers. Move it to
pci_common.c to avoid a broken build when CONFIG_DM_PCI is on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Tim Harvey
378b02d7ed pci: imx: display message if no pcie link
If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was
detected.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-28 12:01:44 +02:00
Tim Harvey
0373a7e91b pci: display header for bus scan
If we are displaying detected PCI devices (CONFIG_PCI_SCAN_SHOW) display
a 'PCI:' header prior to scan.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-05-27 13:35:54 -04:00
Tom Rini
d81572c272 Merge git://git.denx.de/u-boot-mpc85xx 2015-05-05 14:57:23 -04:00
Minghuan Lian
1d0b59a9b0 fsl/pci: Set CFG_READY for PCIe v3.0 and later
Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:23 -07:00
Zhao Qiang
5066e62847 T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:16 -07:00
Bin Meng
81d0b354b0 pci: Remove parameter 'class' of pci_rom_load()
pci_rom_load() does not use its parameter 'class', so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Bin Meng
d57c2f24fc pci: Option rom class is a 24-bit number
We should pass a u32 class number to pci_rom_probe() instead of a u16.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Minghuan Lian
0070459048 pci/layerscape: fix link and class issues to support ls2085a
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
d42bd3453a pci/layerscape: remove unnecessary pcie_layerscape.h
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Simon Glass
a219daeafe dm: x86: pci: Add a PCI driver for driver model
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
36d0d3b4b4 dm: sandbox: pci: Add a PCI emulation uclass
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00
Simon Glass
537849aaa1 dm: sandbox: Add a simple PCI driver
Add a driver which can access emulations of devices and make them available
in sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00
Simon Glass
ff3e077bd2 dm: pci: Add a uclass for PCI
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.

TODO: Add more header file comments to the new parts of pci.h

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00
Simon Glass
aab6724c90 dm: pci: Move common PCI functions into their own file
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:42 -06:00
Minghuan Lian
e4e8cb7138 driver/pci: add Layerscape PCIe driver
The patch adds Freescale Layerscape PCIe driver and provides
up to 4 controllers support.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:50 -08:00
David Feng
6eefd5279c PCI: add 64-bit prefetchable memory support
PCI specification allow prefetchable memory to be 32-bit or 64-bit.
PCI express specification states that all memmory bars for prefetchable
memory must be implemented as 64-bit. They all require that 64 bit
prefetchble memory are suported especially when u-boot is ported to
more and more 64bit processors.

Signed-off-by: David Feng <fenghua@phytium.com.cn>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-16 15:48:26 -05:00
Simon Glass
bc17d8f4ac x86: video: Allow video ROM execution to fall back to the other method
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:43 -07:00
Simon Glass
250e039da8 pci: Add a function to find a device by class
There is an existing function prototype in the header file but it is not
implemented. Implement something similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05 22:16:42 -07:00