Commit graph

70 commits

Author SHA1 Message Date
Simon Glass
23cacd5704 pci: Drop PCI_INDIRECT_BRIDGE
This does not work with driver model so can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13 18:23:13 -04:00
Simon Glass
22137b8d73 pci: ppc: Drop ftpci100 driver
This is not used in U-Boot at present. Drop it and related config options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-06 08:26:48 -04:00
Tom Rini
ac9fa5705c pci: Require DM_PCI
As the migration deadline has passed, require that DM_PCI be used.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:06:08 -04:00
Kunihiko Hayashi
e22c25607b pci: uniphier: Add UniPhier PCIe controller driver
Add PCIe driver for UniPhier SoCs. This PCIe controller is based on
Synopsys DesignWare Core IP.

This version doesn't apply common DW functions because supported
controller doesn't have unroll version of iATU.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14 16:48:08 -04:00
Masami Hiramatsu
3296d52bb5 pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the
PCIe RC and filter out a ghost pcie config.

Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device
is configured by firmware (EDK2), it doesn't re-configure in the kernel.
So as same as EDK2, U-Boot needs to configure it before boot the kernel.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:07:36 -04:00
Green Wan
416395c772 drivers: pci: add pcie support for fu740
Add pcie driver for SiFive fu740, the driver depends on
fu740 gpio, clk and reset driver to do init. Force running at Gen1
for better capatible enumeration.

Several devices are tested:
a) M.2 NVMe SSD
b) USB-to-PCI adapter
c) Ethernet adapter (E1000 compatible)

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-31 16:35:54 +08:00
Stefan Roese
ddafdb9091 mips: octeon: Add Octeon PCIe host controller driver
This patch adds the PCIe host controller driver for MIPS Octeon II/III.
The driver mainly consist of the PCI config functions, as all of the
complex serdes related port / lane setup, is done in the serdes / pcie
code available in the "arch/mips/mach-octeon" directory.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-23 21:03:25 +02:00
Neil Armstrong
2c32c701ea pci: add Amlogic Meson Designware PCIe controller
Add support for the DW PCIe controller found in the Amlogic Meson AXG and
G12 (G12A, G12B, SM1) SoCs.
This uses the common DW PCIe helpers introducted previously.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-15 10:43:17 +08:00
Neil Armstrong
dfadb946f6 pci: add common Designware PCIe functions
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the
Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.

This introduce a "common" DW PCIe helpers file with common code merged from the
dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson.

The following changes will switch the dw_ti and dw_rockchip to use these helpers.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Green Wan <green.wan@sifive.com>
[bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-15 10:43:17 +08:00
Shawn Lin
9ddc0787bd pci: Add Rockchip dwc based PCIe controller driver
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Suneel Garapati
638d705a54 pci: Add PCI controller driver for OcteonTX / TX2
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Srinath Mannam
4848704aef drivers: pcie: add Broadcom IPROC PCIe RC driver
Add support for IPROC PAXC PCIe RC driver.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14 09:43:21 -04:00
Hou Zhiqiang
ed188aa886 pci: layerscape: Add specific config entry for RC and EP mode driver
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
118e58e26e pci: layerscape: Split the EP and RC driver
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Jagan Teki
ad415c80a5 pci: rockchip: Drop legacy PHY driver
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:49 +08:00
Sylwester Nawrocki
7b1c3f6f65 pci: Add driver for Broadcom BCM2711 SoC PCIe controller
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.

The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10 11:49:28 +02:00
Jagan Teki
89f2fa0b5e pci: Add Rockchip PCIe PHY controller driver
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.

The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.

Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.

Example:

grf: syscon@ff770000 {
   compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
   reg = <0x0 0xff770000 0x0 0x10000>;
   #address-cells = <1>;
   #size-cells = <1>;

   pcie_phy: pcie-phy {
       compatible = "rockchip,rk3399-pcie-phy";
       clocks = <&cru SCLK_PCIEPHY_REF>;
       clock-names = "refclk";
       #phy-cells = <1>;
       resets = <&cru SRST_PCIEPHY>;
       drive-impedance-ohm = <50>;
       reset-names = "phy";
       status = "disabled";
   };
};

Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Jagan Teki
99d59069c0 pci: Add Rockchip PCIe controller driver
Add Rockchip PCIe controller driver for rk3399 platform.

Driver support Gen1 by operating as a Root complex.

Thanks to Patrick for initial work.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-22 20:53:20 +08:00
Wasim Khan
1185b229cc pci: layerscape: Common device tree fixup for NXP SoCs
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
5ff7b84084 drivers/pci : enable pcie_layerscape code for lx2160a rev2
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Tom Rini
923e211f8d pci: Only link pci_rom.o in some cases
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
liu hao
e3aafef4cf arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07 18:01:13 -05:00
Heiko Schocher
b61cbbdcab pci: add DM based mpc85xx driver
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30
Ryder Lee
42d37450e5 pci: mediatek: add PCIe controller support for MT7623
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:09:58 -04:00
Sekhar Nori
03c396bb5f pcie: ti: add driver for AM65x PCIe RC
Add driver supporting PCIe root-complex available
on TI's AM65x SoC.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:39 -04:00
Hou Zhiqiang
b89e3d9250 dm: pci: add Freescale PowerPC PCIe driver
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20 10:44:45 +05:30
Tom Rini
c18b103657 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
2019-05-26 20:18:20 -04:00
Hou Zhiqiang
1d341bc4b6 pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
07ce19f5e9 pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Marek Vasut
776abedef4 pci: renesas: Add RCar Gen3 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs.
The PCIe on Gen3 is used both to connect external PCIe peripherals.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21 22:15:31 +02:00
Ley Foon Tan
7c45862f22 pci: intel: Add Intel FPGA PCIe controller driver
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in
rootport mode only, the EP mode is not supported. The driver is tested
with the Intel e1000e NIC driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-08 09:07:35 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Wilson Ding
e51f2b14c4 arm64: a37xx: pci: add support for aardvark pcie driver
This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30 12:52:49 +02:00
Marek Vasut
5f14f7d783 pci: rmobile: Add RCar Gen2 PCIe controller driver
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-27 20:38:53 +01:00
Tuomas Tynkkynen
55acf49eab PCI: Drop CONFIG_TSI108_PCI
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-01-10 08:05:49 -05:00
Tuomas Tynkkynen
3675cb044e PCI: Add driver for a 'pci-host-ecam-generic' host controller
QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06 11:28:12 -04:00
Simon Glass
37b499c43f Drop CONFIG_WINBOND_83C553
This is not used in U-Boot. Drop this option and associated dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:43 -05:00
Hou Zhiqiang
a7294aba08 pci: layerscape: move kernel DT fixup to a separate file
To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:26:24 -08:00
Shadi Ammouri
182ba1a7df pci: mvebu: Add PCIe driver for Armada-8K
This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri <shadi@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:34:33 +01:00
Paul Burton
a29e45a9c4 pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-21 15:04:32 +02:00
Simon Glass
3f4e1e8efc dm: pci: video: Convert video and pci_rom to use DM PCI API
Adjust these files to use the driver-model PCI API instead of the legacy
functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
5e23b8b4a4 dm: pci: Use driver model PCI API in auto-config
At present we are using legacy functions even in the auto-configuration code
used by driver model. Add a new pci_auto.c version which uses the correct
API.

Create a new pci_internal.h header to hold functions that are used within
the PCI subsystem, but are not exported to other drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Simon Glass
3ba5f74a54 dm: pci: Disable PCI compatibility functions by default
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:38 -07:00
Simon Glass
011e948295 dm: pci: Move common auto-config functions to a common file
Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:37 -07:00
Simon Glass
76a8b6a58a dm: pci: Rename pci_auto.c to pci_auto_old.c
This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01 06:26:37 -07:00
Anton Schubert
9c28d61c8e pci: mvebu: Add PCIe driver
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.

Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

This port was done in cooperation with Anton Schubert.

Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-08-17 18:49:43 +02:00
Simon Glass
a219daeafe dm: x86: pci: Add a PCI driver for driver model
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
36d0d3b4b4 dm: sandbox: pci: Add a PCI emulation uclass
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00
Simon Glass
537849aaa1 dm: sandbox: Add a simple PCI driver
Add a driver which can access emulations of devices and make them available
in sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00
Simon Glass
ff3e077bd2 dm: pci: Add a uclass for PCI
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.

TODO: Add more header file comments to the new parts of pci.h

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-16 19:27:43 -06:00