Commit graph

10293 commits

Author SHA1 Message Date
Ang, Chee Hong
bd5581716d arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20 17:12:25 +01:00
Ang, Chee Hong
877ec6ebbd arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20 17:12:25 +01:00
Ang, Chee Hong
8b36ba27ad arm: socfpga: stratix10: Add macros for mailbox's arguments
Add macros for specifying number of arguments in mailbox command.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20 17:12:25 +01:00
Ang, Chee Hong
d99f1e92a2 arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20 17:12:25 +01:00
Neil Armstrong
53904dc7c1 arm: dts: s400: Fix status for eMMC and SDIO ports
Under U-boot, the WiFi SDIO Module should be disabled and the
eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
include file specific for U-Boot that will be included by the build system.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
2018-12-19 16:20:50 +01:00
Tom Rini
d597b26d51 Improvements and fixes or u-boot-rockchip:
- new board: adds rv1108-elgin-r1 board support
 - rk3288-evb: dts: remove 'vmmc' from emmc node
 - rk3399-puma: dts: remove obsolete DTS node 'vcc5v0_host'
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcFpKgAAoJECaAFcEOcohNoPoIAIsUwrwTbaB6/fDaXBoVXPmf
 8IQx6TjFKhs5930civVjnNVBR/19swAVoR8dR6JSGHgjv9C1k6zjEZfcKyi8Gr4J
 NORaNklExXqyBfHr+htHDgJ1OjmAImbNaVhbkGFtD/gELQ9LI1eFfNIDv26ZxDYH
 WKV/EQNbOxyDeOShCxn4GzGjqG0h0mvm/PlFH2s59b5SLAM8Ptg6B7ZRoe+go5fz
 l7nBl/TBG99lJtMpECMIpl3rqpU/JfYy2ONYVerX0w4ZshWjWJg6/m4pwWwLlUNn
 eJR1VsC5DZ6ocfQinFPU9xvjxAYXEy42Li82hFQg9KKs+4uchbKCLYrAiEQd6nk=
 =8Rly
 -----END PGP SIGNATURE-----

Merge tag 'for-master-20181216' of git://git.denx.de/u-boot-rockchip

Improvements and fixes or u-boot-rockchip:
- new board: adds rv1108-elgin-r1 board support
- rk3288-evb: dts: remove 'vmmc' from emmc node
- rk3399-puma: dts: remove obsolete DTS node 'vcc5v0_host'
2018-12-16 20:49:46 -05:00
Otavio Salvador
e11ef3d26e ARM: rockchip: Add rv1108-elgin-r1 board support
Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:

- UART
- eMMC
- USB

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-16 01:30:11 +01:00
Tom Rini
401c254044 Merge branch 'master' of git://git.denx.de/u-boot-usb
- Second half of the USB Gadget DM conversion
2018-12-15 17:49:57 -05:00
Kever Yang
9af1d5ef2f rockchip: rk3288-evb: dts: remove 'vmmc' from emmc node
This is a sync with kernel mainline dts.

The U-Boot eMMC does not need to care about the power for Rockchip
SoCs, because if the board is using eMMC, the power will default on
(for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15 20:56:46 +01:00
Christoph Muellner
1ae5cd0226 rockchip: rk3399-puma: Remove obsolete DTS node 'vcc5v0_host'.
vcc5v0_host and usbhub_enable share gpio4 RK_PA3,
which is a problem during probing (the second probe
will trigger a -EBUSY, when trying to get the gpio handle).

An analysis of the situation shows, that both regulators
are actually describing the same supply.

This patch removes the (currenlty not successful probing)
regulator vcc5v0_host from the DTS and adds the pinctrl-*
setting to usbhub_enable.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15 20:56:26 +01:00
Shawn Guo
655c6d997d poplar: fix boot failure caused by serial driver change
Commit 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
driver for Poplar platform, because the platform falls into the
following strategy category made by the commit.

  Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Before the commit lands, Poplar platform works by statically declaring
pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
in the driver.  But since Poplar also supports device configuration from
device tree, the commit practically drops the flag for Poplar, and hence
breaks the platform from booting.

This patch changes platform code and device tree to initiate pl011
serial device from device tree rather than static declaration, so that
above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
the reported boot failure gets fixed.

Reported-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers")
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-15 11:49:56 -05:00
Jean-Jacques Hiblot
7a43dd7aa6 arm: am33xx: Register USB controllers if DM_USB is used but not OF_CONTROL
When DM_USB is used, either the USB controllers are bound when the DTB
is parsed (when OF_CONTROL is enabled) or they are bound using the
U_BOOT_DEVICES() macro.
In the later case, the platform data is passed in a struct ti_musb_platdata
because it cannot be read from the DTB.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:10 +01:00
Jean-Jacques Hiblot
7d98dbcc3d usb: musb-new: Add support for DM_USB
Enable DM for USB peripheral in the musb-new driver.
Also make sure that the driver can be used in the SPL.
This implies that:
* the driver must work with and without the OF_CONTROL option. That
in turn, implies that the platform data can be passed in a struct
ti_musb_platdata or be read from the dtb
* usb.o is linked in the SPL if host support is enabled

Another change is that the driver does not fail to bind (and stop the boot
process) if one of the child driver does not bind. Reporting the error is
enough. This kind of error would appear if the port is configured in the
DTS but the driver is not activated in the config.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:10 +01:00
Jean-Jacques Hiblot
4ea0711104 dts: am4372: Enable USB1 in SPL
USB1 can be used by the romboot on all am4372 platforms to download a
firmware (SPL in our case).
It makes sense to enable USB1 in the SPL to download u-boot.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:10 +01:00
Jean-Jacques Hiblot
894f002f20 dts: Add a u-boot specific dtsi file for the am4372
This file is used to override the values found in am4372.dtsi
Use it to fix the "compatible" options for the controllers used
to support the USB (parent bus and syscons).

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:09 +01:00
Jean-Jacques Hiblot
d53653f3f9 ARM: dts: k2g-evm: enable USB0 and USB1
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:09 +01:00
Simon Glass
93a98a6ff3 dm: exynos: sound: Convert to use driver model
Update snow's device tree and config to use driver model for sound. Also
update the others as best we can.

Spring does not appear to have audio support in the kernel. The smdk5250
and smdk5420 boards use a wolfson codec which I cannot test with. So the
only boards that is tested and known to work are snow, pit and pi.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:36:30 -07:00
Simon Glass
482e585bdf exynos: Add support for exynos5420 i2s pinmux
Allow setting the i2s pinmux correctly on exyno5420 so that i2c can be
used on that SoC. Also rename EXYNOS_AUDSS to something consistent with
other naming.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:36:30 -07:00
Simon Glass
cf9007ce88 exynos: Add proid_is_exynos542x() for common 542x
Add a convenience function for any Exynos 542x chip.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:36:30 -07:00
Simon Glass
d6cadd5918 dm: sound: Add conversion to driver model
Move the existing hardware drivers over to use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:36:29 -07:00
Simon Glass
51b06dc40b dm: sound: exynos: Correct codec bus addresses
For snow the codec is at address 0x11 on the i2c bus, in 7-bit format.
The device tree and code are in 8-bit format (i.e. shifted left one bit).
Fix both. Fix pit in a similar way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:32:49 -07:00
Simon Glass
c275a08bc4 snow: Expand U-Boot size
Now that we have EFI, etc. enabled, U-Boot is larger than it was. Expand
the region allocated for it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-13 16:32:49 -07:00
Felix Brack
bfaaacd3b2 arm: am335x-pdu001: Move from embedded to separate DTB
There is no need for an embedded device tree for this board so let the
build process generate a separate u-boot.dtb file instead.

Signed-off-by: Felix Brack <fb@ltec.ch>
2018-12-12 12:14:23 -05:00
Tom Rini
d94604d558 Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL
 nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg
 rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB
 Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana
 KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv
 9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB
 vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S
 B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w
 2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z
 xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H
 agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII
 urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4=
 =aT7d
 -----END PGP SIGNATURE-----

Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10 17:19:59 -05:00
Tom Rini
8bf3c2442b Improvements:
- init DRAM for RK322x in SPL
 - add FAN53555 PMIC/regulator driver
 - update MicroCrystal RV3029 driver to Kconfig and sync from Linux
 - add bootcount uclass and first DM-driver for bootcount
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcDiw9AAoJECaAFcEOcohNEa8H/RBWLbVQjHPXf6EjchXgVcSs
 Gc+g2QmKZbN21XebfzBpCuZj62NROTWUcrPtor17yEBiMM1xPfe1vC7qtbkR6USj
 VTt1JHeyGx3XafkkUpeps382YPfuaNqtabjwZaXlmeE4/VLbXQPE7x4tC4fdWus4
 9K3OGQgRNFirn+RIZ7dQWtCby82PEC3cHkPc/n82cVHofcDsgKYK9mPpfcCn/gWF
 A4Fa9cx4pjeaMrBHKjcByCiFmwYBPc97Hqzz64oHOdQP0g3h04ko+2w5DdwdeHVV
 jKNcvkHESF4m1RGjrTbLEhy1f5UuOfcA1ise/cDX4pjXlBdwxHmvqT5vsE0MQzI=
 =5sHL
 -----END PGP SIGNATURE-----

Merge tag 'for-master-20181210' of git://git.denx.de/u-boot-rockchip

Improvements:
- init DRAM for RK322x in SPL
- add FAN53555 PMIC/regulator driver
- update MicroCrystal RV3029 driver to Kconfig and sync from Linux
- add bootcount uclass and first DM-driver for bootcount
2018-12-10 10:19:09 -05:00
Tom Rini
7ff485c68b Merge branch 'master' of git://git.denx.de/u-boot-i2c
- DM_I2C_COMPAT removal for all ti platforms from Jean-Jacques Hiblot
- Fix in i2c command help output from Chirstoph Muellner.
2018-12-10 07:16:33 -05:00
Tom Rini
7504e9e75f Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-12-10 07:15:55 -05:00
Tom Rini
e7463b37a1 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-12-10 07:15:41 -05:00
Tom Rini
48d299a799 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DWC3 and UDC cleanup
2018-12-10 07:15:12 -05:00
Philipp Tomsich
eff43904b7 rockchip: rk3399-puma: enable fan53555 regulators in DTS
Now that we have FAN53555 support, we can enable the regulators in our
DTS.  To make these easier to identify on the U-Boot commandline, we
rename them to the names of the voltage rails they control.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-10 10:04:45 +01:00
Jean-Jacques Hiblot
40ecdbc648 dra7: Allow selecting a new dtb after board detection.
The DRA7 platforms requires that the dtb used in the SPL really matches the
platform  to have the best MMC performances.
To detect the board type/version an I2C EEPROM is read. This requires that
DM is initialized before the detection. As a consequence we must reset the
DM after the board detection is a new dtb would better match the platform.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 07:27:25 +01:00
Jean-Jacques Hiblot
1514244cc1 ti: remove usage of DM_I2C_COMPAT and don't disable DM_I2C in SPL
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
when all I2C "clients" have been migrated to use the DM API.
This a step in that direction for the TI based platforms.
Build tested with buildman:
buildman -dle am33xx ti omap3 omap4 omap5 davinci keystone

boot tested with:
am335x_evm, am335x_boneblack, am335x_boneblack_vboot (DM version),
am57xx_evm, dra7xx_evm, k2g_evm, am437x_evm

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 07:15:21 +01:00
Jean-Jacques Hiblot
2b30b38b26 omap: detect the board after DM is available
In order to use DM_I2C, we need to move the board detection after the
early SPL initialization.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:14:47 +01:00
Jean-Jacques Hiblot
69dab2be8e dts: am43x: omap5: Add node for I2C in SPL
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:13:35 +01:00
Jean-Jacques Hiblot
0e6e67c667 am335x: Register the I2C controllers if DM_I2C is used.
If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
because OF_CONTROL is not used in the SPL.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:12:42 +01:00
Jean-Jacques Hiblot
5f97ae6814 i2c: omap24xx_i2c: Use platdata to probe the device
This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:11:18 +01:00
Vignesh R
bca09ce4b0 i2c: omap24xx_i2c: Move away from SoC specific headers for reg offset
Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-12-10 06:09:34 +01:00
Tom Rini
8cb8c0c6a8 Merge git://git.denx.de/u-boot-marvell
- Sync DDR training with Marvell code for Armada 38x by Chris
- Misc updates to Armada 38x Helios4 board by Aditya
2018-12-09 08:40:49 -05:00
Aditya Prayoga
5ca84c6dd2 arm: mvebu: helios4: Reset uSOM onboard phy during board init
Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet
PHY.

This patch depend on
net: mvneta: Add GPIO configuration support
[URL: https://patchwork.ozlabs.org/patch/1007736/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Aditya Prayoga
8d7d97e2d1 arm: mvebu: helios4: Enable SPI flash support
Enable SPI flash support under U-Boot and SPL. The ENV size and offset,
ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16

To create U-Boot image for SPI flash, user would need to replace
* CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
* CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Aditya Prayoga
c209a65e9e arm: mvebu: helios4: Enable I2C and IO Expander
Enable Marvell I2C driver and I2C IO expander. Set default bus to
external I2C bus. Define I2C aliases in device tree so it can be
recognized by the driver.

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Tom Rini
c49aff3e66 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various axp209 fixes
- Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC
2018-12-07 19:02:01 -05:00
Olliver Schinagl
c970e8954f sunxi: pmic_bus: Decrease boot time by not writing duplicate data
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-07 22:24:33 +05:30
Simon Goldschmidt
a9024dc18e arm: socfpga: imply SPL options instead of select
For a small SPL, it should be possible to build without SPI(-flash) drivers
or wihout MMC drivers.

For this to work, we have to change from 'select'ing options to 'imply'ing
them.

With this change, I can have SPL trimmed to my hard-wired starting method
(SPI-NOR or MMC) while still including all drivers in U-Boot.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-12-07 16:32:01 +01:00
Jean-Jacques Hiblot
d0af9eb501 dts: dra7x: make ocp2scp@4a080000 compatible with simple-bus
This is required when DM_USB is used, to bind the USB phys.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 16:31:46 +01:00
Jean-Jacques Hiblot
687ab54560 usb: introduce a separate config option for DM USB device
Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2018-12-07 16:31:45 +01:00
Takeshi Kihara
5055a4e900 ARM: rmobile: Fix to enable icache early in Gen3
This patch fixes the problem that u-boot will not start unless icache is
enabled early.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Takeshi Kihara
10854bcc25 ARM: rcar_gen3: fix protection area access error
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF)
set by DBSC from the map area.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Hiroyuki Yokoyama
23b9b36ae3 ARM: rcar_gen3: fix protection area access error at Cortex-A53
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Felix Brack
fdce9d35dc arm: dts: am33xx: Sync dts with Linux 4.20.0
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 08:13:51 -05:00
Adam Ford
8a15bdb040 ARM: DTS: da850-evm: Re-sync da850-evm.dts from Linux 4.20
There has been some natural evolution of the device tree, so
resync with 4.20

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
ae67a9b330 ARM: dts: da850-lcdk: Sync from Linux 4.20
Re-synce the device tree files from Linux 4.20

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
031288abe9 ARM: DTS: da850: Sync from Linux 4.20
Re-sync with 4.20 due some some natural evolution.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
343b606261 ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.20
Migrate some small device tree fixes from Linux 4.20.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
faef5b376e ARM: DTS: Resync LogicPD SOM-LV with Linux 4.20
There have been a few fixes to the device trees, so this
re-syncs the dts/dtsi files with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:49 -05:00
Adam Ford
5792f0d8be ARM: DTS: Resync am3517-evm.dts with Linux 4.20
The DTS file for the AM3517 had the incorrect CD polarity.  Resync with
the fixed DTS file from Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:48 -05:00
Patrice Chotard
b2f84e37e2 gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.h
To allow access to this define by other driver, move
it into gpio.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Patrice Chotard
dbf928dd26 gpio: stm32f7: Add gpio bank holes management
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.

For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Álvaro Fernández Rojas
e9e8d80d8c serial: bcm6858: remove driver and switch to bcm6345
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:46 -05:00
Álvaro Fernández Rojas
47b1cbaf02 arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:46 -05:00
Felix Brack
2aadff0feb arm: am335x-pdu001: Enable CONFIG_BLK and CONFIG_DM_MMC
This patch enables CONFIG_BLK as well as CONFIG_DM_MMC for the PDU001
board. It depends on Patrice Chotard's patch 'power: regulator: denied
disable on always-on regulator' which prevents power cycling the vmmc
supply. Without this patch the board will not boot as vmmc is
unfortunately used by other board components, not just eMMC and micro SD
card. Furthermore my patch 'dts: am335x-pdu001: Fix polarity of card
detection input' is required to boot from external micro SD card. Without
this patch no SD card will be detected and hence booting will fail.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 08:13:46 -05:00
Felix Brack
ae0a157b38 dts: am335x-pdu001: Fix polarity of card detection input
When a micro SD card is inserted in the PDU001 card cage, the card
detection switch is opened and the corresponding GPIO input is driven
by a pull-up. Hence change the active level of the card detection
input from low to high.

Signed-off-by: Felix Brack <fb@ltec.ch>
2018-12-07 08:13:45 -05:00
Eugen.Hristev@microchip.com
bbaeb7ac22 ARM: at91: lds: add test for SPL binary size and bss size
Add test for the SPL binary size and the bss section size.
This will throw an error at build time if the SPL sections
do not fit in the designated RAM area, thus avoiding oversizing the SPL.

Based on original work by Wenyou Yang.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-12-07 08:13:44 -05:00
Benjamin Gaignard
075b0185b6 pinctrl: stm32: make pinctrl use hwspinlock
Protect configuration registers with a hardware spinlock.

If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Benjamin Gaignard
9119f547d3 hwspinlock: add stm32 hardware spinlock support
Implement hardware spinlock support for STM32MP1.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
d6fdec211f armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
6252faa0da armv8: lsch3: Add support of serdes3 module
Some lsch3 based SoCs like lx2160a contains three
serdes modules.
Add support for third serdes protocol in lsch3

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
8ec42856f1 armv8: dts: fsl-ls2080a: add sata node support
One ls2080a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
3e586ee307 armv8: dts: fsl-ls1088a: add sata node support
One ls1088a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
539e0cb6dc armv8: dts: fsl-ls1046a: add sata node support
One ls1046a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
ade32bb473 armv8: fsl-layerscape: add support of MC framework for TFA
Add support of MC framework for TFA
Make MC framework independent of boot source.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2e17cb8a42 armv8: sec_firmware: return job ring status as true in TFABOOT
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
339fb297d4 armv8: sec_firmware: change el2_to_aarch32 SMC ID
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17,
it is applicable to both TFA and non-TFA boot.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
56db948b85 armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
5a73ec6169 armv8: layerscape: skip OCRAM init for TFABOOT
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
681d489e62 armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2141d250f5 armv8: fsl-layerscape: bootcmd identification for TFABOOT
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
[YS: remove unnecessary braces]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:36 -08:00
Rajesh Bhagat
b6c97f4d94 armv8: layerscape: remove EL3 specific erratas for TFABOOT
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.

ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663,
SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942,
SYS_FSL_ERRATUM_A010165

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
4c41738462 armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:26 -08:00
Rajesh Bhagat
535d76a121 armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable
execution from DDR.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
e350648046 armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
bb50569dc4 armv8: layerscape: Enable routing SError exception
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Manivannan Sadhasivam
467877341a rockchip: rk3399: Add Ficus EE board support
Add board support for Ficus EE board from Vamrs. This board utilizes
common Rock960 family support.

Following peripherals are tested and known to work:
* Gigabit Ethernet
* USB 2.0
* MMC

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
[Reworked based on common Rock960 family support]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
Manivannan Sadhasivam
07f7687869 rockchip: rk3399: Add Rock960 CE board support
Add board support for Rock960 CE board from Vamrs. This board utilizes
common Rock960 family support.

Following peripherals are tested and known to work:
* USB 2.0
* MMC

This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which
is being used on the board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
Manivannan Sadhasivam
1bad5e1492 rockchip: rk3399: Add common Rock960 family from Vamrs
Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs.
It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition)
96Boards.

Below are some of the key differences between both Rock960 and Ficus
boards:

1. Different host enable GPIO for USB
2. Different power and reset GPIO for PCI-E
3. No Ethernet port on Rock960

The common board support will be utilized by both boards. The device
tree has been organized in such a way that only the properties which
differ between both boards are placed in the board specific dts and
the reset of the nodes are placed in common dtsi file.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[Added instructions for SD card boot]
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2018-12-06 16:04:49 +01:00
Randy Li
2c9050cd3d arm: dts: rockchip: add some common pin-settings to rk3399
Those pins would be used by many boards.

Commit grabbed from Linux:

commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f
Author: Randy Li <ayaka@soulik.info>
Date:   Thu Jun 21 21:32:10 2018 +0800

    arm64: dts: rockchip: add some common pin-settings to rk3399

    Those pins would be used by many boards.

    Signed-off-by: Randy Li <ayaka@soulik.info>
    Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
York Sun
d171c70716 move data structure out of cpu.h
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04 08:30:23 -08:00
Marek Vasut
00e4b57e9e ARM: rmobile: Set environment variable containing CPU type
Set environment variable 'platform' containing the CPU type.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-04 09:21:07 +01:00
Marek Vasut
66582cf6da ARM: rmobile: Enable MMC extensions
Enable extended MMC commands and GPT partition table support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
cbff9f80ce ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6
Synchronize DTs with mainline Linux 4.19.6 ,
commit 96db90800c06d3fe3fa08eb6222fe201286bb778

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
3b255531b6 ARM: dts: rmobile: Sync Gen2 DTs with Linux 4.19.6
Synchronize DTs with mainline Linux 4.19.6 ,
commit 96db90800c06d3fe3fa08eb6222fe201286bb778

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
4e96b693ee ARM: dts: rmobile: Extract i2c6 on M2W Porter
The i2c6 node is missing in mainline Linux thus far, pull it
into U-Boot specific DT until it hits mainline Linux, to make
syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
47179e5737 ARM: dts: rmobile: Extract SCIF2 node on E3 Ebisu
The SCIF2 node is not in Linux 4.17 DTs on E3, pull it into U-Boot
specific DT extras until it hits mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
6bdb7a80cb ARM: dts: rmobile: Extract SDHI nodes on E3 Ebisu
The SDHI nodes are not in Linux 4.17 DTs in E3, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
1bce3ec801 ARM: dts: rmobile: Extract SDHI extras on H3, M3W, M3N Salvator-X
The SDHI nodes are missing features supported in upstream U-Boot,
like mode support properties. Pull the extras into U-Boot specific
DT until it hits mainline Linux, to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
750a147b3c ARM: dts: rmobile: Extract SDHI extras on H3 and M3W ULCB
The SDHI nodes are missing features supported in upstream U-Boot,
like mode support properties. Pull the extras into U-Boot specific
DT until it hits mainline Linux, to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
d2038b26e7 ARM: dts: rmobile: Extract CPLD node on H3 and M3W ULCB
The CPLD node is missing in Linux 4.17 DTs on H3/M3W ULCB, pull the
node into U-Boot specific DT until it hits mainline Linux, to make
syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
1172ade967 ARM: dts: rmobile: Extract AVB node extras on V3M Eagle
The AVB node is not complete in Linux 4.17 DTs on V3M Eagle, pull the
AVB node extras into U-Boot specific DT until they hit mainline Linux,
to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
830b94f768 ARM: dts: rmobile: Extract SDHI nodes on M3N
The SDHI nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
f529bc551b ARM: dts: rmobile: Extract USB nodes on M3N
The USB nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
8c7d9e1f62 ARM: dts: rmobile: Extract RPC node to u-boot specific DT
The RPC DT bindings are still work in progress. Extract the RPC DT node
from the DT to allow easier update and so it can be replaced once the DT
bindings are stable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
a89929bbb3 ARM: dts: rmobile: Add soc label to Gen3
Add label to the /soc node, so it can be referenced from the U-Boot DTs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Tom Rini
0a3d59e010 Xilinx changes for v2019.01
microblaze:
 - Use default functions for memory decoding
 - Showing model from DT
 
 zynq:
 - Fix spi flash DTs
 - Fix zynq_help_text with CONFIG_SYS_LONGHELP
 - Tune cse/mini configurations
 - Enabling cse/mini testing with current targets
 
 zynqmp:
 - Enable gzip SPL support
 - Fix chip detection logic
 - Tune mini configurations
 - DT fixes(spi-flash, models, clocks, etc)
 - Add support for OF_SEPARATE configurations
 - Enabling mini testing with current targets
 - Add mini mtest configuration
 - Some minor config setting
 
 nand:
 - arasan: Add subpage configuration
 
 net:
 - gem: Add 64bit DMA support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlwFUAkACgkQykllyylKDCHtIACeO2G+jfSPxIjsyuPWbRup4e+A
 H5UAn3knKDNJ3VVidqO1C5o8Ye5JePZF
 =lW3g
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support
2018-12-03 19:30:54 -05:00
Tom Rini
f388e3bed7 Patch queue for efi - 2018-12-03
This release is fully packed with lots of glorious improvements in UEFI
 land again!
 
   - Make PE images more standards compliant
   - Improve sandbox support
   - Improve correctness
   - Fix RISC-V execution on virt model
   - Honor board defined top of ram (fixes a few boards)
   - Imply DM USB access when distro boot is available
   - Code cleanups
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJcBYKAAAoJECszeR4D/txgBgwQALmYioI67R5/Iizpv7bg+rIQ
 0TyPKZHmfHtVjGHd5X4X+9NBsoaSKqGnoI12bJ+V9hIMuiu5qFKyM3icTOOJ6LI6
 wggnvMWZl5nfZmdEgETHTmaZkQZzKwhzbftGlGf2j19FdDk1OOI7hRNLeaIZUTv0
 VHiUV68PP/1Of1y7iqB5jij1wTUHWlCufKjGXELP0bAXx86/tecgCuvjBihXizz/
 sMsCxEF8++pb5l/l4yFEkKd5rr5D/ZkKMLR4KniZVq2qP1S4calolP14ykHN+a/l
 uKP4e4GDuYyrgXXTNRFhVTlaAn18bmvxH4ialnpYVZKRtfsdHPHQXfqmgf8ZgJPE
 JK3mmG6eLCbBPeND2Yz3b7G/Ec04z+RJXx0hriyLdejLgp5jM9SBtygiz6FmQLpQ
 VfDJNEWV7ot6Ejou55O0d9u5ATF0jAd4tikmsrStWWZOVHvie6nG0wFYiRxnWCKP
 sid0p7lWSUKEl0sAvA0LglNMzd4tCAq7vtkfLj/BVrDc9Jpir9CVJ13ppXIGk1HC
 YIGWLo0uXAGC9wgRE7ZgGCKtQ6VFZRbSiJQOowi4MrHzHXH218oSNz2w25tAVTBw
 le2WbxlGNYhV1xnoWMks1GTdWGQDCXdfBAhfzRIvQq2kz4z9V8hzpnVDIk2ZL3L1
 o3nqUatR0ZVXPcinf+Ke
 =6o9t
 -----END PGP SIGNATURE-----

Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-12-03

This release is fully packed with lots of glorious improvements in UEFI
land again!

  - Make PE images more standards compliant
  - Improve sandbox support
  - Improve correctness
  - Fix RISC-V execution on virt model
  - Honor board defined top of ram (fixes a few boards)
  - Imply DM USB access when distro boot is available
  - Code cleanups
2018-12-03 17:52:40 -05:00
Tom Rini
ec0d0d8742 Merge branch 'master' of git://git.denx.de/u-boot-sh
- MMC fixes for R-Car Gen3
2018-12-03 17:51:45 -05:00
Yegor Yefremov
67c145a836 arm: baltos: move the board to CONFIG_BLK
Use DM for both MMC and USB subsystems and use dedicated DTS
for U-Boot configuration.

Disable SPL support for GPIO and remove EVMSK leftover for
DDR power control via GPIO.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-03 10:44:10 -05:00
Loic Devulder
8973d81658 ARM: meson: Add regmap support for clock driver
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.

DTS files are synchronized from Linux 4.19.

Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-03 13:34:21 +01:00
Marek Vasut
0be621aebd ARM: dts: rmobile: Enable HS400 on Salvator-X, ULCB, Ebisu
Enable the HS400 support in DT on H3, M3W, M3N Salvator-X(S)
and ULCB boards as well as E3 Ebisu board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
d0e0bbe7d1 ARM: dts: rmobile: Enable SDR modes on E3 Ebisu
Add regulators and pinmuxes for SDHI0 and SDHI1 SD and microSD
slots on E3 Ebisu and mark them as capable of up to SDR104 mode
of operation. With the SDHI fixes in place, it is now possible
to use SDR104.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
286ded3394 ARM: dts: rmobile: Enable SDR104 on Salvator-X and ULCB
Enable SDR104 modes on M3W and H3 boards. With the SDHI fixes
in place, it is now possible to use SDR104.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
ca3163ddb7 ARM: dts: rmobile: Add eMMC DS pinmux
Add pinmux entry for the eMMC DS line, as it is connected on these boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Heinrich Schuchardt
81ea00838c efi_loader: PSCI reset and shutdown
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.

The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.

The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.

As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:37 +01:00
Bin Meng
fb8ebf52a4 arm: efi: Generate Microsoft PE format compliant images
Per Microsoft PE Format documentation [1], PointerToSymbolTable and
NumberOfSymbols should be zero for an image in the COFF file header.
Currently the COFF file header is hardcoded on ARM and these two
members are not zero.

This updates the hardcoded structure to clear these two members, as
well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we
can generate compliant *.efi images.

[1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:36 +01:00
Tom Rini
c1d6e0bbfd Improvements:
- RK3188 USB-UART functionality
 - errors triggering a hard-stop in SPL on the RK3399 are reported
 - Rockchip RV1108 (SoC) support
 - MicroCrystal RV3029 (RTC) DM driver
 
 Fixes:
 - RK3188 early UART setup
 - limit SD-card frequency to 40MHz on the RK3399-Q7
 - MIPI fixes
 - RK3399 CPUB clock initialisation
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcAab4AAoJECaAFcEOcohNx8gH/0OuW443gsA8Ty0rXpCvbzSi
 UejfBfqljX4tYcUrgABVdMd2WdUyQ6rSoVgnX6mvfToCxd51L2CQiimrTJRQp/ZQ
 yCrwC8iFYwgmyM/0UnnjRa03WJvYBi3McWWIxQy7ZywQcZkdIuyn6t5AbcRppGMF
 67G0ft9KRwB+dMcgdRuikDThZRhAWZ30MdY4LFZvyGWupuv/mdpyYhjHYyv05CVf
 BvaUqRFkt86GBAW7Hq+OahH1t/xuZBcPJdt8GC40Blgfmle2uvZOIpoSEezVwFXm
 qKSj5FSSVQ9XtMeWwWvHLUxKSua0pIX5d7HmK9WqcsUIePDbzth8i+/BdA+5AD4=
 =EYJx
 -----END PGP SIGNATURE-----

Merge tag 'for-master-20181130' of git://git.denx.de/u-boot-rockchip

Improvements:
- RK3188 USB-UART functionality
- errors triggering a hard-stop in SPL on the RK3399 are reported
- Rockchip RV1108 (SoC) support
- MicroCrystal RV3029 (RTC) DM driver

Fixes:
- RK3188 early UART setup
- limit SD-card frequency to 40MHz on the RK3399-Q7
- MIPI fixes
- RK3399 CPUB clock initialisation
2018-12-01 14:17:27 -05:00
Kever Yang
17e5f3a426 rockchip: rk3188: use board_debug_uart_init() for UART io init
Sync with other rockchip SoCs, use board_debug_uart_init() to
init default UART iomux.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 22:00:11 +01:00
Christoph Muellner
af765a49ba rockchip: rk3399: Initialize CPU B clock.
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.

The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).

Tested on RK3399-Q7 on Haikou base board.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00
Otavio Salvador
8177c5c452 ARM: dts: rockchip: Add rv1108 USB OTG pinctrl
This adds the definitions need to use the USB OTG in rv1108
board. This has been tested using USB Mass Storage to export and
program a eMMC device.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00
Otavio Salvador
303cbd2141 ARM: rockchip: rv1108: Add a board_usb_init for USB OTG
Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Otavio Salvador
a8819e9a9e ARM: dts: rockchip: Add rv1108 eMMC pinctrl
This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Otavio Salvador
5d2cb15c77 ARM: rockchip: rv1108: Sync clock with vendor tree
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Philipp Tomsich
765246a18c rockchip: rk3399-puma: reduce sd card max-frequency to 40MHz
Some SanDisk Ultra cards trigger intermittent errors on detection
resulting in an -EOPNOTSUPP, when running at 50MHz.

Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module (for voltage translation between the on-module
voltages and the 3.3V required on the card-edge) don't handle clock
rates at or above 48MHz properly. This change reduces the maximum
frequency on the external SD-interface to 40MHz (for a safety margin
of 20%).

Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Philipp Tomsich
adbca53a3a rockchip: rk3399: spl: always report errors triggering a hard stop
The RK3399 SPL has two cases that may end in a hard-stop: if either
the pinctrl can not be initialised or if the DRAM fails to initialise.
Both have previously not triggered an error message unless DEBUG was
defined (i.e. both used debug() to print the error).

This converts both error messages to be printed using pr_err() to
ensure that some output points to the cause of the hard-stop.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
6c69ed19f9 rockchip: rk3188: fix early uart setup
Commit 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions
into pinctrl-driver") moved the iomux settings out of the grf header
to prevent conflicts with the iomux definitions of other rockchip socs.

This also breaks the early uart setup, as the iomux for uart2 are needed.
To fix that just put the tiny amount of needed iomux definitions next to
the early uart code.

Fixes: 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
5b5ca4c0d4 rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up to mark grf as maybe unused:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Tom Rini
d814ff34a1 Merge git://git.denx.de/u-boot-marvell
- Some Kirkwood boards converted to DM_SPI by Chris
- New Armada-385 SoC revision printed by Chris
- Ethernet enable on mcbin by Baruch
- Support 2 DRAM banks on Armada-8k boards by Baruch
2018-11-30 11:20:03 -05:00
Chris Packham
d997ad034b ARM: mvebu: add revision id for Armada-385 B0
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a
hardware errata enabling RGMII to work when the Ethernet voltage is
configured to 3.3V.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30 10:58:10 +01:00
Baruch Siach
eff26e4804 arm: mvebu: mcbin: dts: enable 1G network interface
Describe the 1Gb network interface with on-board 88E1512 PHY.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30 10:58:10 +01:00
Michal Simek
ee97a9996a arm64: zynqmp: Add mini mtest configuration
This configuration is useful when you want to run small u-boot and
perform DDR memory test to make sure that DDR is properly configured.
It is use for board bringup because alternative u-boot memory tests is
quite good.
Configuration is running out of OCM.

As is done for others mini configurations 0x80 bytes for variables is
enough and only default variables are stored there.

Alternative memtest is enabled and also 2GB of DDR via DTS files.
Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init()
from zcu102 for testing purpose.
In case of size issue this can be moved to SPL configuration as is done
for mini_qspi configuration but it is not a problem now.

Log:
U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100)

Model: ZynqMP MINI
Board: Xilinx ZynqMP
DRAM:  WARNING: Initializing TCM overwrites TCM content
2 GiB
EL Level:       EL3
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Tom Rini
6d4a3ff264 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-11-29 16:36:53 -05:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJb/AwoAAoJEHfc29rIyEnR2dMQANCsuWQzKASCLgUzeL/KWhQ8
 gj1YEVGbS0meQ35hNo0hL6qfN4VkjazawyWnb40HVVADBjil42QuxN9rncovg69Q
 ZvPEo4XYNCkDzOU3UmoR2rjxxGICVFY6GCOuNbqzvB2x4gWJmoUeByqewKW2g2Zp
 jyjbzYvJ+r8wLtUFbdqaGvsHHC8hiIkjyeaqdXUc6NHJrGYasRuOsCO92bEioYC1
 XPh76c2ABAnbzJy7GArdlBbDOQrQxoEskVeP47ZjiPywXxGCkgHaRSXaUKzpz30G
 8MrA5AciL6pmurmsM0APlgvJwL7qaX1P6NxiJ+12prWWfAk1ZC2/MEKVZY+gO/CF
 vUAyzhus1oJ5JjccCngy/1ftkIReueSbUrzGYFvqhihs9g4QyRpi7F5MDKX0MvP2
 uk+XXStXs+rOZ2YdMFlV8l6G12TijcViZVmVHdh8qdl4t8WFlv7gENVUM+0mhyu2
 x5OsoYz5w2h9hCh/CB3oIZfyJBe5VZVHZ2fWIRZJ72J7toUGMewlKYQq2LOv7A9q
 w6vRGnza3fSPUZgYenznohaeo9vXG/WX7cNSPQiNBoiGeC+Y2ko5NHe2MIEnUD4c
 amp21KA6rWnWeHHvDbwo5DJ+NhCd6uMgkiZDLCuiTtns1/a03l0V6kgOvQLIBjhK
 KxBWBn6+rDPq1wJxhxab
 =Oo1g
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Simon Goldschmidt
30bade20a6 arm: socfpga: fix SPL booting from fpga OnChip RAM
This patch prevents disabling the FPGA bridges when
SPL or U-Boot is executed from FPGA onchip RAM.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
e8dd60d489 arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
This fixes the board's dts to supply SPL with QSPI info.

The EBV Socrates board has DIP switches to boot from SD card or
QSPI, so let's fix its defconfig to work for both cases.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
c402e81702 dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)

Adapt board dts files that are not in Linux to keep their old
behaviour.

Change licenses to SPDX.

(Patman warnings/errors are in 1:1 copied files from Linux)

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
2a3a99932b spi: cadence_qspi: use "cdns,qspi-nor" as compatible
Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
dd8ee8ea2a arm: socfpga: make config structs const
There are two config structs left in wrap_sdram_config.c that can
be made const.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Michal Simek
6bd13ee94e arm64: zynqmp: Setup clock-output-names for si570 chips
If there are more instances of si570 clock-output-names property
should be used for differentiation of clock output.
The patch is adding this optional properties for all zynqmp boards with
si570 chip.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
8418d2deb8 arm64: zynqmp: Disable ltc2952 poweroff chip
This chip is on the board but handling should be done via firmware not
via Linux driver. Changing status property to keep it in the tree to
describe it instead of removing this node completely.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
d1fb3d024e arm64: zynqmp: Fix sdhci clock in emmc0 mini configuration
Add missing clocks property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
0ed45f0025 arm64: zynqmp: Wire spi-flash compatible string with flashes
Enable reading tx and rx buswidth from DT via spi-uclass.
To get these from uclass spi-flash compatible string has to be added
to flash node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Siva Durga Prasad Paladugu
9cd26aaf39 arm64: zynqmp: Define and enable qspi node for DC4 board
DC4 board has qspi on it hence define and enable
qspi node for it.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:29:58 +01:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Weijie Gao
361e13f1d5 arm: MediaTek: add basic support for MT7623 boards
This adds a general board file based on MT7623 SoCs from MediaTek.

As this u-boot is loaded by MTK proprietary preloader, there is no
low level initializtion codes.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
cbd2fba1ec arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
d84982dbfa arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
376ac00dc3 arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:49 -05:00
Marcin Niestroj
627d74c79b ARM: dts: am335x-chiliboard: add /chosen/stdout-path
Add that node path in u-boot overlay dtsi file for now to keep
am335x-chiliboard.dts in sync with Linux.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:13 -05:00
Marcin Niestroj
e067379f88 ARM: dts: am335x-chili*: add chiliSOM and chiliboard DTS files
Import chiliSOM and chiliboard dts files from Linux v4.19. They will
be used after transition to driver model and device-tree based boot.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:13 -05:00
Andrew F. Davis
a0106c82d6 ARM: armv7: Add early stack for erratum workarounds
Some erratum workarounds call into C code before the stack
is setup, this can lead to values pushed onto the stack
being lost, firewall exceptions, and other undefined behavior.

Setup a temporary stack to allow these functions to work
correctly.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2018-11-26 22:52:12 -05:00
Lokesh Vutla
ccdb7c2255 armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:11 -05:00
Tom Rini
c06088b360 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-11-26 15:52:47 -05:00
Neil Armstrong
d96a782d09 ARM: meson: Add boot device discovery
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.

When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.

When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.

In this mode, we can load different binaries that can be used by U-boot
like a script image file.

This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.

The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.

[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
b890acc743 ARM: meson: factorize common code out amlogic's boards
Now we have moved all the Amlogic board support to common generic board code,
we can move the identical board_init() and ft_board_setup() functions to
weak functions into the board-common mach-meson file.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
b72794e37e board: amlogic: add support for S400 board
The S400 board is the Amlogic AXG SoC reference board including :
 - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
 - 1GB DDR4 SDRAM
 - 10/100 Ethernet
 - 2 x USB 2.0 Host
 - eMMC
 - Infrared receiver
 - SDIO WiFi Module
 - MIPI DSI Connector
 - Audio HAT Connector
 - PCI-E M.2 Connectors

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
f6eb68b978 clk: Add clock driver for AXG
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
78a08019cd ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
Synchronize the Amlogic AXG Device Tree files and bindings include from
the recent Linux 4.20-rc1, because it includes patches fixing support for
U-boot.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
485bba395e ARM: meson: Add support for AXG family
This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
33e3378091 ARM: meson: rework soc arch file to prepare for new SoC
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
96a739b460 ARM: rework amlogic configuration
Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving
the board Kconfig into the mach-meson Kconfig to make it easier to add
new boards for a SoC architecture and add a custom config header or custom
board handler for a platform.

This drops the board CONFIGs and the duplicate boards configs headers in
favor of a single meson64.h config header.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
d54e03b612 board: amlogic: factorise gxbb boards
The nanopi-k2 and the odroid-c2 are similar enough to be supported
by the same u-boot board. This change use odroid-c2 u-boot board
for the nanopi-k2 as well. Dedicated defconfig are kept to customize
the names and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Neil Armstrong
302987b6c5 board: amlogic: move khadas-vim2 as q200 ref board
The Khadas vim2 derive from amlogic s912 reference design (Q200).

This patch moves the khadas-vim2 board support to a generic Q200 board,
while keeping a dedicated defconfig to customize the names and device tree.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Jerome Brunet
8bbfb40e57 board: amlogic: remove p212 derivatives
The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive
from amlogic s905x reference design (P212).

All the code in these board is a copy/paste from the p212, which is
tedious to maintain. This change use p212 u-boot board for all these
boards, while keeping a dedicated defconfig to customize the names
and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Jerome Brunet
32caa1e2f1 ARM: meson: clean-up platform selection
Even if multiple board are selected through Kconfig, u-boot will only
compile one. This makes sense since compiling these targets will export
global symbols, such as board_init()

The change rework amlogic Kconfig so only one board may be selected at
a time

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Michal Simek
850e7795cd arm64: zynqmp: Enable SPL_SEPARATE_BSS by default
BSS section was all the time separated for SPL but this symbol wasn't
enabled. It is necessary to have it enabled for OF_SEPARATE
configuration where DTB is appended to u-boot with DTB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:55 +01:00
Michal Simek
f3289d1f0e arm64: zynqmp: Reflect emmc controller ID in model in DT
Make sense to add controller ID to model name to have it visible through
the logs to know which controller is used by which configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:55 +01:00
Siva Durga Prasad Paladugu
c25e804dd8 arm: zynq: cse_qspi: Fix overwriting spi-rx-bus-width property
spi-rx-bus-width property is part of flash, so it should be moved
to flash node from qspi node. This patch fixes the incorrect read
of spi-rx-bus-width property by moving it to flash node.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:54 +01:00
Michael Trimarchi
aa09a071c3 sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-22 13:24:15 +05:30
Vasily Khoruzhick
0e21a2ffb3 sunxi-mmc: use new mode on both controllers on A64
Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22 13:20:16 +05:30
Vasily Khoruzhick
2a8882ecef sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled

Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-22 13:19:19 +05:30
Simon Glass
8729b1ae2c misc: Update read() and write() methods to return bytes xfered
At present these functions return 0 on success. For some devices we want
to know how many bytes were transferred. It seems useful to adjust the API
to be more like the POSIX read() and write() functions.

Update these two methods, a test and all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-20 19:14:22 -07:00
Rabeeh Khoury
5bbf36af7f ARM: mvebu: dts: add Clearfog GT-8K
The SolidRun Clearfog GT-8K is based on Armada 8040.

https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k

The config file is identical to the Macchiatobin one
(mvebu_mcbin-88f8040_defconfig) with only the default device-tree
changed.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:44 +01:00
Baruch Siach
2b4d964718 arm64: mvebu: a8k: autodetect RAM size
Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from
external DIMM. Hard coding the RAM size in the device-tree is not
convenient. Fortunately, the ATF that initializes the RAM knows the size
of RAM, and U-Boot can query the ATF using a SMC call.

The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is
mapped at 4G. This leaves a 1G hole between 3G and 4G for IO
peripherals. Use a second bi_dram[] entry to describe the higher RAM
area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more
than 3GB RAM.

This code in this commit is mostly taken from downstream Marvell U-Boot
code by Grzegorz Jaszczyk.

Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
b335e91bd1 linux/sizes.h: sync from kernel
The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr:
reduce module randomization range to 4 GB).

Include linux/const.h for the _AC macro.

Drop a local SZ_4G definition in tegra code.

Cc: Tom Warren <twarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
5c8fd32b22 Use _AC and UL macros from linux/const.h
Drop the _AC and UL macros from common.h. Linux headers is the original
source of this macro, so keep its definition in the same header.

Update existing users of these macros to include const.h directly.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Lokesh Vutla
00b34e9937 armv7r: dts: am654: Add initial support
Add R5 specific dts for am654-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
2d0eba3a45 arm: dts: k3: Sync dts from Linux
Sync the k3-am654 specific dts files from Linux next with tag
20181019. This changes are in queue for Linux v4.20-rc1

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
59ebf4afa6 armv7R: K3: am654: Add support for triggering ddr init from SPL
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support
for triggering DDR initialization from board_init_f().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
a3501a4a44 armv7R: K3: am654: Add support to start ATF from R5 SPL
Considering the boot time requirements, Cortex-A core
should be able to start immediately after SPL on R5.
Add support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
890b2e750d armv7R: K3: am654: Add support for generating build targets
Update Makefiles to generate:
- tiboot3.bin: Image format that can be processed by ROM.

Below is the tiboot3.bin image format that is required by ROM:

		 _______________________
		|	 X509		|
		|     Certificate	|
		| ____________________	|
		| |		      |	|
		| | u-boot-spl.bin    |	|
		| |		      |	|
		| |___________________|	|
		|_______________________|

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
23f7b1a776 armv7R: K3: am654: Enable MPU regions
Enable MPU regions for AM654 evm:
- Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable
- Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc
- Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc
- region3-15: Disabled

With this dcache can be enabled either in SPL or U-Boot.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
06bda1259f ram: Introduce K3 AM654 DDR Sub System driver
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-16 16:51:58 -05:00
Klaus Goger
ba08afe837 arm: Make arch specific memcpy thumb-safe.
The current arch implementation of memcpy cannot be called
from thumb code, because it does not use bx instructions on return.
This patch addresses that. Note, that this patch does not touch
the hot loop of memcpy, so performance is not affected.

Tested on MXS (arm926ejs) with and without thumb-mode enabled.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-16 16:51:57 -05:00
Adam Ford
c3b89468fc ARM: DTS: Resync am3517-evm.dts with Linux 4.19
Some minor changes have been made to the AM3517-evm and the underlying
am3517.dtsi files.  This patch re-sync's the DTS and DTSI files with
Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-11-16 13:34:37 -05:00
Philippe Reynes
786dc91492 bcm968580xref: add initial support
This add the initial support of the broadcom reference
board bcm968580xref with a bcm6858 SoC.

This board has 512 MB of ram, 256 MB of flash (nand),
2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-11-16 13:34:35 -05:00
Philippe Reynes
40b59b0586 bcm6858: add initial support
This add the initial support of the broadcom bcm6858 SoC family,
only the cpu, dram and uart are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-11-16 13:34:35 -05:00
Prasanthi Chellakumar
1473f6ac88 arm: at91: wdt: Convert watchdog driver to dm/dt
Convert the Watchdog driver for AT91SAM9x processors to support
the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG"
to new "CONFIG_WDT_AT91" Kconfig option.

Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
eb13dddd2c ARMv8: SError exception handling in PSCI exception vectors
Allow platform vendors to handle SError interrupt exceptions from
ARMv8 PSCI exception vectors by overriding this weak function
'plat_error_handler'.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
c0f3296f83 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Kconfig option to allow all External Abort and SError exception
taken to EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
a7aab5bcb5 ARMv8: Enable all asynchronous abort exceptions taken to EL3
Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:33 -05:00
Tom Rini
1d6edcbfed - virtio implementation and supporting patches
- DM_FLAG_PRE_RELOC fixes
 - regmap improvements
 - minor buildman and sandbox things
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlvsxt8RHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIrebPtQgAxR8bKdTNODUuVrw5OUIl40ziKQvNIlG5
 uiVsQLDI7Cd9D3Yls8yNffXqkNcQj+0/MJa38UZsm32c/uR4PU0zyFxpz4mwgyXk
 ZMrJ15AEAxf4IOHjbh52sNgR2mw+PeP9A3NO5LnZAMd/rnRF2MgBTy28FvjsBlNn
 z4OUjUpNv4ePND0QQ1EoGPlYotYPASEw8iK1pc5L+Rwq/ponAnNqegKIxQtiMugY
 kLtuFe0JJ704T20UkwYvI8LsnuB50ANRLLMyy5JLy1UtCpS24cc86ml49IKk3pqb
 v4GbnMI67s7S+Imzm4A7Mg8fgGnkkpLqacI3gnlpbIPkLrqRM2C20g==
 =RORj
 -----END PGP SIGNATURE-----

Merge tag 'pull-14nov18' of git://git.denx.de/u-boot-dm

- virtio implementation and supporting patches
- DM_FLAG_PRE_RELOC fixes
- regmap improvements
- minor buildman and sandbox things
2018-11-16 08:37:50 -05:00
Tom Rini
6f44333018 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-11-14 18:25:34 -05:00
Bin Meng
4854ebc57e arm: stm32mp: Remove DM_FLAG_PRE_RELOC flag
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.

To mitigate this potential impact, the following changes are
implemented:

- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
  only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
  is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-14 09:16:28 -08:00
Bin Meng
6f3327658b arm: qemu: Add a Kconfig in the board directory
This adds a Kconfig file in the board directory, so that some
board-specific options can be specified there.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Tom Rini
208ecbad2e Merge branch 'next'
This brings in the u-boot-net PR from Joe.
2018-11-14 11:30:07 -05:00
Icenowy Zheng
7d121a8ea4 sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD
DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:17:06 +05:30
Jagan Teki
e6b16e7852 board: allwinner: sun50i-h6: Add Orangepi Lite2 support
OrangePi Lite2 is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- AP6356S Wifi/BT
- USB 2.0, USB 3.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-13 22:13:09 +05:30
Jagan Teki
d45a07aaca arm64: allwinner: h6: Add common orangepi nodes into dtsi
Based on the information from hardware schematics and orangepi
vendor orangepi H6 boards, One Plus and Lite2 shares common nodes
like axp805, uart, mmc0 etc. The common differences between them is
- One Plus, has Ethernet
- Lite2, has Wifi, USB3, CSI port.

So, add common orangepi nodes into sun50i-h6-orangepi.dtsi so-that
it case use on respective orangepi h6 board dts files.

Cc: zhaoyifan <zhao_steven@263.net>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-13 22:13:01 +05:30
Vasily Khoruzhick
b972831c3c sunxi: DT: add support for Pinebook
Pinebook is a laptop produced by Pine64, with USB-connected keyboard,
USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP
bridge from Analogix.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:10:03 +05:30
Vasily Khoruzhick
31a4ac4d79 sun50i: A64: add support for R_I2C controller
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:09:10 +05:30
Vasily Khoruzhick
20940ef2a3 mmc: sunxi: add support for automatic delay calibration
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:07:39 +05:30