Commit graph

5 commits

Author SHA1 Message Date
Joe Hershberger
0adb5b761f net: cosmetic: Name ethaddr variables consistently
Use "_ethaddr" at the end of variables and drop CamelCase.
Make constant values actually 'const'.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:32 -06:00
Kishon Vijay Abraham I
4564faeafb ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c
Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.

Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-04-16 15:08:36 -04:00
Lokesh Vutla
802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
Masahiro Yamada
7eb3923695 omap: beagle_x15: add MAINTAINERS
Commit 1e4ad74b87 (beagle_x15: add board support for Beagle x15)
missed to add board/ti/beagle_x15/MAINTAINERS.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Felipe Balbi <balbi@ti.com>
2015-01-12 09:38:47 -05:00
Felipe Balbi
1e4ad74b87 beagle_x15: add board support for Beagle x15
BeagleBoard-X15 is the next generation Open Source
Hardware BeagleBoard based on TI's AM5728 SoC
featuring dual core 1.5GHZ A15 processor. The
platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60),
separate LCD port, video In port, 4GB eMMC, uSD,
Analog audio in/out, dual 1G Ethernet.

For more information, refer to:
http://www.elinux.org/Beagleboard:BeagleBoard-X15

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:39 -05:00