These options are required to be present in RFC 4578 compliant DHCP
requests. They give more information to DHCP servers to allow serving
different DHCP responses to different systems based on client
architecture, client capabilities, UUID, or vendor.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Add pxe command, which is intended to mimic PXELINUX functionality.
'pxe get' uses tftp to retrieve a file based on UUID, MAC address or IP
address. 'pxe boot' interprets the contents of PXELINUX config like file
to boot using a specific initrd, kernel and kernel command line.
This patch also adds a README.pxe file - see it for more details on the
pxe command.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
With these documented, we can start pushing towards standardizing their
use across boards.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Existing ctype checks are implemented using a 256 byte lookup table,
allowing each character to be in any of 8 character classes. Since there
are 8 existing character classes without the blank class, I implemented
isblank without using the lookup table. Since there are only two blank
characters - tab and space - this is a more reasonable approach than
doubling the size of the lookup table to accommodate one more class.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
This will be used first by the pxe code, but is intended to be
generic and reusable for other jobs in U-boot.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
commit a45dde2293 changed the dm9000
direct register access to standard IO. This should work
on the ColdFire platform as there are corresponding macros for
the LE devices. But the hardware settings on some ColdFire boards had
swapped the byte order which make the original macros such as out_le16
cannot work. To avoid changing the common io access code on ColdFire
platform, the DM9000_BYTE_SWAPPED define was added to make the dm9000 use
__raw* IO access on some ColdFire boards.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
The function kw_gpio_is_valid returns zero on success, so
adapt the error check accordingly.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Dieter Kiermaier <dk-arm-linux@gmx.de>
Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.
Acked-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
mx3fb.c was based on CONFIG_LCD and is moved by this patch to
CONFIG_VIDEO, which has greater freedom in selecting videomodes
even at runtime.
This renders the accumulating list of display defines
(CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
these may be setup through env variables:
uboot> setenv mydisplay 'video=ctfb❌240,y:320,depth:16,mode:0,pclk:185925,
le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0'
uboot> setenv videomode ${mydisplay}
This commit also fixes the board config files for qong and
imx31_phycore boards as needed. The videomode settings of
previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS
now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased
to make the frame buffer allocation working with the changed
driver.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Pixel format defines must be available for boards to set up
the right display. Move them and export in a new file.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The framebuffer driver for MX5 is based on CONFIG_LCD.
In the current implementation, there is a serious bug
because the required memory is allocated before
relocation, but the driver knows only later which is
the resolution of the display. The patch switches the driver
to CONFIG_VIDEO and the memory is allocated by the driver itself.
We also need to switch the vision2 board code and config file
in the same commit so that this commit will be bisectable.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Update the Freescale DIU video driver (fsl_diu_fb.c) to use linux/fb.h.
Some data structures from this header file were just copied into
fsl_diu_fb.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
In the recent dropping of !NET_MULTI code (commit e2a53458a7),
I misread the logic in include/net.h. Some of it was used by NET_MULTI
code as glue between the multi/non-multi worlds for cpm2 boards.
Rather than restore the block of code, push the logic to the board config
headers where it all belongs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 'master' of git://git.denx.de/u-boot-video:
video: Moving mx3fb.c to CONFIG_VIDEO
mx31: make HSP clock for mx3fb driver available
MX5: Make IPU display output and pixel format configurable
VIDEO: MX5: export pix format
VIDEO: MX5: Switch MX5 to CONFIG_VIDEO
video: update the Freescale DIU driver to use linux/fb.h
If compressed data is located in sectors at the end of the flash and
it's offset + input stream size > 0xFFFFFFFF, the uncompressing time
is very long, since processing of the stream is done bytewise (and
not blockwise) due to overflow in inflate_fast() while calculation
and checking for enough input available.
Check for this overflow condition and limit the available stream
input size to the actually max. possible input size. This fixes
the problem.
The issue is easily reproduceable by placing a gziped bitmap in flash,
e.g. at FFF80000, and running 'bmp' commands like 'bmp info FFF80000'
or 'bmp display FFF80000'. The uncompressing can take up to 3 sec.
whereas it should normaly take a fraction of a second. If the
'splashimage' environment variable points to this address, the
booting time also increases significantly.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.
Acked-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.
MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The command auto-completion does not work on architectures relying
on CONFIG_NEEDS_MANUAL_RELOC like MIPS. Cause is the missing function
pointer fixup for cmd_tbl_t::complete function in fixup_cmdtable().
This patch adds the missing pointer fixup in case of CONFIG_AUTO_COMPLETE
is defined.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
A delay of approximately 250 ms after PCI bus reset in
pci_mpc5xxx_init() is needed to recognize the Coral-PA
controller on the graphic extention board.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
PCI cards might need some time after reset to respond. On some
boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted
at pci_init_board() time, so we currently can not use available
"pcidelay" option for waiting before PCI bus scan since this
waiting takes place before calling pci_init_board(). By moving
the pcidelay code to the new location using of the "pcidelay"
option is possible on mpc5200 or mpc8260 based boards, too.
Since pci_hose_scan() could be called multiple times, restrict
the function to wait only during its first call and to ignore
pcidelay for any further call (as pointed out by Matthias).
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Add axi_ethernet driver for little-endian Microblaze.
RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs.
Only one MAC can work in one time.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Setup RX/TX ping-pong buffer for every emaclite IP separately.
The next patch move initialization directly to board code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
* 'master' of git://git.denx.de/u-boot-fdt:
powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
fdt: update fdt_alloc_phandle to use fdt_get_phandle
fdt: check for fdt errors in fdt_create_phandle
fdt: Add a do_fixup_by_path_string() function
Function fdt_create_phandle() conveniently creates new phandle properties
using both "linux,phandle" and "phandle", so it should be used by all code
that wants to create a phandle.
The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually. Instead, change it to use
fdt_create_phandle().
Signed-off-by: Timur Tabi <timur@freescale.com>
The device tree compiler, dtc, can use "phandle" and/or "linux,phandle"
properties to specify the phandle for any node. By default, it uses
both, but "linux,phandle" is deprecated. One day, we'd like to stop using
"linux,phandle", but U-boot needs to support both properties equally
first.
fdt_alloc_phandle() generates a unique phandle, but it was only checking
the "linux,phandle" properties. Instead, we use fdt_get_phandle(),
which checks both properties automatically. This ensures that we
support dtbs that only use "phandle".
The side-effect is that fdt_alloc_phandle() now takes twice as long, since
it has to check for two properties instead of one in each node that it
searches.
Signed-off-by: Timur Tabi <timur@freescale.com>
fdt_create_phandle() was ignoring errors from fdt_set_phandle(). If an
error occurs, print an error message and return 0, which is an invalid
phandle. We also need to change the return type for fdt_create_phandle()
to indicate that it cannot return an error code.
Signed-off-by: Timur Tabi <timur@freescale.com>
The do_fixup_by_path_string() will set the specified node's property to the
value contained in "status". It would just be an inline wrapper for
do_fixup_by_path() that calls strlen on the argument.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
With older compilers (gcc-4.2.x) we run into issues that resulting image
is too large. We can save a bunch of space by removing the video support.
In general video support on these boards is a nice to have since it
requires a PCIe add-on card.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P3041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P5020 has 10 qman portals, we need to configure all of them:
* As there are only 2 physical cores sdest can only be 0 or 1
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
