3 commits

Author	SHA1	Message	Date
Murali Karicheri	6c343825dd	ARM: keystone: ddr3: workaround for ddr3a/3b memory issue ... This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>	2014-09-17 21:06:56 -04:00
Hao Zhang	101eec50f0	keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 ... Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>	2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan	0b86858956	keystone: ddr3: add ddr3.h to hold ddr3 API ... It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>	2014-07-25 16:26:09 -04:00