Commit graph

80332 commits

Author SHA1 Message Date
Patrick Delaunay
a46dce2817 ram: stm32mp1: add support of STM32MP13x
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 10:41:16 +02:00
Patrick Delaunay
ae3e2c2bf7 board: stm32pm1: add stm32mp13 board support
Add stm32mp15x prefix to all STM32MP15x board specific functions,
this patch is a preliminary step for STM32MP13x support.

This patch also adds the RCC probe to avoid circular access with
usbphyc probe as clk provider.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 10:41:16 +02:00
Dinesh Maniyam
32e0379143 ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
d192adafeb drivers: cache: ncore: Disable snoop filter
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
5474fb894c arm: dts: socfpga: stratix10: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
7f85330782 arm: dts: socfpga: agilex: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:04 +08:00
Dinesh Maniyam
373c1428a0 arch: arm: socfpga: timer_s10: Override udelay for secure section
Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:26:52 +08:00
Patrick Delaunay
cf1d0fd4c1 pinctrl: stm32: add support of STM32MP135
Add support for "st,stm32mp135-pinctrl" for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
46f9eb5dcc arm: stm32mp: support 2 MAC address for STM32MP13
Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in  STM32MP13x family: STM32MP133 and STM32MP135.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
960debbe3c arm: stm32mp: add support of STM32MP13x
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
741090c510 arm: stm32mp: add CONFIG_STM32MP15_PWR
Add config CONFIG_STM32MP15_PWR to handle the
access to regulators managed by the PWR driver defined in
pwr_regulator.c

This driver is only used in U-Boot by STM32MP15x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
d8b78fd632 arm: stm32mp: add sub config Kconfig.15x
Add sub Kconfig for each SOC in the STM32 CPU family.

It is a preliminary step to introduce a new SOC in the STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
647d319cc9 arm: stm32mp: add choice for STM32MP SOC family
Add mandatory choice for SOC support in ARCH_STM32MP.

This patch is a preliminary step for new SOC introduction
in STM32MP family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
6df271a70f arm: stm32mp: move code for STM32MP15x
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
3865a7ec95 arm: stm32mp: move the get_otp helper function in bsec
As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
2ff0866b45 configs: stm32mp1: move SUPPORT_SPL in STM32MP15x
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:58:21 +02:00
Patrick Delaunay
a82abb15a8 ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family based on v5.18-rc2

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:58:21 +02:00
Marek Vasut
4f71c80b0d ARM: dts: stm32: Add DHCOR based DRC Compact board
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
cb6d857db2 ARM: dts: stm32: Add alternate pinmux for SPI2 pins
Add another mux option for SPI2 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
3577cc0632 ARM: dts: stm32: Add alternate pinmux for CAN1 pins
Add another mux option for CAN1 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
9b87f12953 ARM: dts: stm32: Add alternate pinmux for UART5 pins
Add another mux option for UART5 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
fb6284b5af ARM: dts: stm32: Add alternate pinmux for UART4 pins
Add another mux option for UART4 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
40beedb052 ARM: dts: stm32: Add alternate pinmux for UART3 pins
Add another mux option for UART3 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Patrick Delaunay
8b91f28bc8 stm32mp: stm32prog: fix the last character of dfu_alt_add third parameter
The third parameter of dfu_alt_add(), the string description of alternate,
is build in stm32prog_alt_add() with a unnecessary character ';' at the
end of the string.

This separator was required in the first implementation of
dfu_alt_add() but is no more needed in the current implementation;
this separator is managed only in dfu_config_interfaces() which call
dfu_alt_add() for this parameter without this separator.

And since the commit 53b406369e ("DFU: Check the number of arguments
and argument string strictly"), this added character cause an error when
the stm32prog command is executed because the third parameter of
dfu_alt_add() must be a string with a numerical value; 's' must be NULL
in the result of call in dfu_fill_entity_mmc():
  third_arg = simple_strtoul(argv[2], &s, 0);

Fixes: 53b406369e ("DFU: Check the number of arguments and argument string strictly")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:30:19 +02:00
Marek Vasut
3c07d639ed net: Fix discuss discard typo
Replace discuss with discard, that is what happens with packet with
incorrect checksum. Fix the typo.

Fixes: 4b37fd146b ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2022-06-16 18:51:07 -04:00
Peng Fan
7e41abad9b tools: binman: install btool
btool is needed after install binman to system.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-16 15:22:55 -04:00
Corentin LABBE
2f51f946e3 board: ti: am335x: eth_cpsw should depend on CONFIG_NET
The origin of this patch is the breaking of am335x-hs boot
due to commit e41651fffd ("dm: Support parent devices with of-platdata")
HS boards have less SRAM for SPL and so this commit increased memory usage beyond am335x limit.
This commit added 10 driver binding pass and am335x boot only if one pass is done.
SPL try to do more than one pass due to eth_cpsw failing.
Since HS SPL does not need network (and NET is already disabled in config),
the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled.

Signed-off-by: Corentin LABBE <clabbe@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew Davis <afd@ti.com>
2022-06-16 15:22:55 -04:00
Andre Przywara
ce9c579e2b armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-16 15:22:55 -04:00
Heiko Thiery
b11b5afa6a arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
With the move to use DM_CLK the boards uart stops working. The used
properties are not supported by the imx8mq clock driver. Thus
the correct baudrate cannot be selected. Remove this properties here and
the board can start with working uart. Keep it in the main dts because
linux handles these porperties fine.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-06-16 15:22:55 -04:00
Andre Przywara
81755b8c20 usb: host: ehci-generic: Make resets and clocks optional
The generic EHCI binding does not *require* resets and clocks
properties, and indeed for instance the Allwinner A20 SoCs does not
need or define any resets in its DT.

Don't easily give up if clk_get_bulk() or reset_get_bulk() return an
error, but check if that is due to the DT simply having no entries for
either of them.

This fixes USB operation on all boards with an Allwinner A10 or A20 SoC,
which were reporting an error after commit ba96176ab7:
=======================
Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2)
probe failed, error -2
=======================

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-16 15:22:55 -04:00
Miquel Raynal
2ac0baab4a fs/squashfs: sqfs_read: Prevent arbitrary code execution
Following Jincheng's report, an out-of-band write leading to arbitrary
code execution is possible because on one side the squashfs logic
accepts directory names up to 65535 bytes (u16), while U-Boot fs logic
accepts directory names up to 255 bytes long.

Prevent such an exploit from happening by capping directory name sizes
to 255. Use a define for this purpose so that developers can link the
limitation to its source and eventually kill it some day by dynamically
allocating this array (if ever desired).

Link: https://lore.kernel.org/all/CALO=DHFB+yBoXxVr5KcsK0iFdg+e7ywko4-e+72kjbcS8JBfPw@mail.gmail.com
Reported-by: Jincheng Wang <jc.w4ng@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Jincheng Wang <jc.w4ng@gmail.com>
2022-06-16 15:22:55 -04:00
Tom Rini
e744bf3a4b odroid_xu3: Fix board environment variable
When migrating CONFIG_CONS_INDEX to Kconfig, on this platform we changed
what "board" evaluated to in the environment.  This in turn meant that
we would no longer try and find the correct fdtfile via the normal
distro boot logic.  Fix this by overriding board in the default
environment, as done on other platforms where CONFIG_SYS_BOARD is not
what we want to be in the board environment variable.

Fixes: f76750d111 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
Reported-by: Gabriel Hojda <ghojda@yo2urs.ro>
Tested-by: Gabriel Hojda <ghojda@yo2urs.ro>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-16 15:22:55 -04:00
Andrey Zhizhikin
101a0f71e4 .gitignore: add files produced by b4
b4 utility [1] is introduced by Linux Kernel developers and used to
fetch patches and patch series from lore.kernel.org and is proven
to be useful for U-Boot development. Detailed usage of the tool can be
read under post from the original author [2].

This tool fetches files from the list and populates the source folder
with additional files (*.cover and *.mbx) which are not ignored by git
and shown as newly added files.

Add those file patterns into .gitignore file, so they can be safely
skipped during changes attestation.

Link: [1]: https://pypi.org/project/b4/
Link: [2]: https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-16 15:22:55 -04:00
Christian Gmeiner
761157d310 arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.

Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-06-16 15:22:54 -04:00
Christophe Leroy
48f44de8b4 Update email address and company name
This patch updates my email address and company name.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2022-06-16 15:22:54 -04:00
Stefan Roese
41b2182af7 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
While working on an LX2160 based board and updating to latest mainline
I noticed problems using the HW accelerated hash functions on this
platform, when trying to boot a FIT Kernel image. Here the resulting
error message:

   Using 'conf-freescale_lx2160a.dtb' configuration
   Trying 'kernel-1' kernel subimage
   Verifying Hash Integrity ... sha256Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty
 error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
ERROR: can't get kernel image!

Testing and checking with Gaurav Jain from NXP has revealed, that this
alignment check is not necessary here at all. So let's remove this
check completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gaurav Jain <gaurav.jain@nxp.com>
Cc: dullfire@yahoo.com
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-06-16 15:22:54 -04:00
Tom Rini
98c4828740 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next 2022-06-16 09:27:43 -04:00
Tom Rini
9abfbef57f u-boot-imx-20220616
-------------------
 
 Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR)
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYqrb/g8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76ZylgCbBgeOnA1pVAh9uqHNtDdu7LLiKBgAn2s8UAUL
 ppY8i8tzzI20OH+Z1k8R
 =lA7L
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20220616' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220616
-------------------

Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
2022-06-16 08:38:46 -04:00
Marek Vasut
163863d572 arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script
Clean up in ubiload script. Unmount UBIFS from which kernel image was
loaded and detach UBI on which the UBIFS is located, otherwise message
similar to the following is printed just before booting kernel:

Removing MTD device #7 (rootfs) with use count 1
Error when deleting partition "rootfs" (-16)

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tien Fong Chee  <tien.fong.chee@intel.com>
2022-06-16 16:11:06 +08:00
Tien Fong Chee
39bbcc341b ddr: altera: Stratix10: Use phys_size_t for memory size
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:58 +08:00
Tien Fong Chee
ee06c5390f ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:44 +08:00
Yau Wai Gan
f70e00fa7d arm: dts: socfpga: stratix10: Update MMC smplsel value
This new MMC sample select value is obtained from running
tests on multiple Stratix 10 boards and proven working.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:02:26 +08:00
Tom Rini
fd27812e52 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic 2022-06-15 23:11:30 -04:00
Tom Rini
488d30a1e9 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-mmc 2022-06-15 23:10:17 -04:00
Tien Fong Chee
166e5b82a3 intel: n5x: ddr: update license
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15 17:48:22 +08:00
Marek Vasut
1a558fafbb spi: nxp_fspi: Fix clock imbalance
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(),
where the IP clock are initially disabled. Drop the second disabling of
clock to prevent clock enable/disable imbalance reported by clock core:

"
clk qspi_root_clk already disabled
"

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-06-15 11:34:38 +02:00
Loic Poulain
12a29d3b85 mmc: fsl_esdhc_imx: Implement wait_dat0 mmc ops
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time.

Before (using grabserial):
[0.000001 0.000001] U-Boot SPL 2021.04-xxxx
[0.028257 0.028257] DDRINFO: start DRAM init
[0.028500 0.000243] DDRINFO: DRAM rate 3000MTS
[0.304627 0.276127] DDRINFO:ddrphy calibration done
[0.305647 0.001020] DDRINFO: ddrmix config done
[0.352584 0.046937] SEC0:  RNG instantiated
[0.374299 0.021715] Normal Boot
[0.374675 0.000376] Trying to boot from MMC2
[1.250580 0.875905] NOTICE:  BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9
[1.251985 0.001405] NOTICE:  BL31: Built : 08:02:40, Apr 12 2022
[1.522560 0.270575]
[1.522734 0.000174]
[1.522788 0.000054] U-Boot 2021.04-xxxx

After:
[0.000001 0.000001] U-Boot SPL 2021.04-xxxx
[0.001614 0.001614] DDRINFO: start DRAM init
[0.002377 0.000763] DDRINFO: DRAM rate 3000MTS
[0.278494 0.276117] DDRINFO:ddrphy calibration done
[0.279266 0.000772] DDRINFO: ddrmix config done
[0.338432 0.059166] SEC0:  RNG instantiated
[0.339051 0.000619] Normal Boot
[0.339431 0.000380] Trying to boot from MMC2
[0.412587 0.073156] NOTICE:  BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b
[0.414191 0.001604] NOTICE:  BL31: Built : 10:35:26, Apr  6 2022
[0.700685 0.286494]
[0.700793 0.000108]
[0.700845 0.000052] U-Boot 2021.04-xxxx

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15 15:39:59 +09:00
Loic Poulain
d6ad5a0af9 mmc: Add support for wait_dat0 callback
There is no wait_dat0 mmc ops, causing operations waiting for data
line state change (e.g mmc_switch_voltage) to fallback to a 250ms
active delay. mmc_ops still used when DM_MMC is not enabled, which
is often the case for SPL. The result can be unexpectly long SPL
boot time.

This change adds support for wait_dat0() mmc operation.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15 15:39:56 +09:00
Patrick Delaunay
d72267049b env: mmc : align erase address and size on erase_grp_size
On eMMC device, the erase_grp_size > 1 so the address and size for the
erase block command in env/mmc.c can be unaligned on erase group size and
some strange trace occurs and the result is not guarantee by MMC devices.

The SD-Card behavior doesn't change as erase_grp_size = 1 for SD-Card.

For example, on eMMC present on STM32MP15C-EV1 and before the patch:

  STM32MP> env erase

  Erasing Environment on MMC...

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

  16 blocks erased: OK

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

  16 blocks erased: OK
  OK

After this patch:
  STM32MP> env erase
  Erasing Environment on MMC...
  1024 blocks erased at 0x2000: OK
  1024 blocks erased at 0x2000: OK
  OK

Here the 2 copies of U-Boot environment are in the same devices Erase
group: it is erased twice.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-15 15:34:18 +09:00
Patrick Delaunay
212875e707 mmc: fix error message for unaligned erase request
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.

for example:
  - start = 0x2000 - 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

But no issue when the end address is not aligned, for example
  - start = 0x2000 - 2 * 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-15 15:34:18 +09:00