Commit graph

105 commits

Author SHA1 Message Date
Michal Simek
00fb945cf5 arm64: zynqmp: Move pinctrl node under firmware node
Pinctrl is handled via firmare interface that's why move it there without
reg property and new compatible string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
ba19690287 arm64: zynqmp: Fix GIC compatible property
dtbs_check is showing warning around GIC compatible property as
interrupt-controller@f9010000: compatible: ['arm,gic-400', 'arm,cortex-a15-gic']
is not valid under any of the given schemas

Similar change has been done also by Linux kernel commit 5400cdc1410b
("ARM: dts: sunxi: Fix GIC compatible")

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
04437dea7c arm64: zynqmp: Sync DP subsystem
Sync DP subsystem with the latest state in Xilinx U-Boot repository.
This binding hasn't been approved in mainline Linux but it is much better
than ancient version which this patch removes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Ashok Reddy Soma
d9872d8b47 arm64: dts: zynqmp: Add clk cells for sdhci
Add clock-cells and clock-output-names for sdhci0 and sdhci1.
These are needed for linux sdhci driver from 5.4 version onwards.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
87b0176fbf arm64: zynqmp: Remove second copy of reset-controller
Reset controller is handled via firmware that's why it should be the part
of firmware node. Origin solution hasn't been removed when above change was
applied by commit b07e97b4ba ("arm64: zynqmp: Use reset header in
zynqmp.dtsi").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Nava kishore Manne
21620990cf arm64: zynqmp: Sync zynqmp fpga manager with mainline
Sync zynqmp fpga manager with mainline.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
d31f1c9236 arm64: zynqmp: Update Copyright years to 2020
Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
b94a3c2ebe arm64: zynqmp: Sync gpio-controller name location
Sync location with mainline kernel.
Added by Linux kernel commit 75926f07baae
("arm64: dts: zynqmp: Add missing gpio-controller to ps gpio").

Fixes: 0b33e0b156 ("arm64: zynqmp: Add missing gpio property to dtsi")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:56 +01:00
Michal Simek
096d7f5b3e arm64: dts: zynqmp: Fix node names which contain "_"
s/_/-/ for node names.

It fixes warnings like this:
... Warning (node_name_chars_strict): /cpu_opp_table:
Character '_' not recommended in node name ...

Issues reported by make dtbs W=12

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:55 +01:00
Rob Herring
8e3501ec90 arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-01-14 09:05:55 +01:00
Michal Simek
2038e46f48 arm64: zynqmp: List lpd watchdog in dtsi
There are use cases where lpd watchdog can be configured for APU use. By
design this IP should be listed in zynqmp.dtsi to make sure that node is
properly enabled by DTG.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:03 +02:00
Michal Simek
332996ce18 arm64: zynqmp: Use power header in zynqmp.dtsi
Use power header and add power-domains property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:03 +02:00
Michal Simek
b07e97b4ba arm64: zynqmp: Use reset header in zynqmp.dtsi
Wire reset-controller and use macros from reset header.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
dead6f67c7 arm64: zynqmp: Use backward compatible string for gem
Add backward compatible string for gem ("cdns,gem").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
039c740d66 arm64: zynqmp: Switch to xlnx-zynqmp-clk header
Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Naga Sureshkumar Relli
c3a34b8006 arm64: zynqmp: Update nand device tree node properties
This patch updates the nand device tree node properties as per
updated driver.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
631ed92a30 arm64: zynqmp: Fix DT style for ipi mailbox
Remove additional empty space.

Fixes: 95497afada ("arm64: zynqmp: add firmware and mailbox node to DT")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Ibai Erkiaga
95497afada arm64: zynqmp: add firmware and mailbox node to DT
The following patch adds a mailbox node and firmware node to following the
mainline DT.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:55:11 +02:00
Amit Kucheria
9a06ed88f4 arm64: dts: Fix various entry-method properties to reflect documentation
The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".

Linux commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.

Linux docs:
Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Mounika Grace Akula
3c8ee337eb arm64: zynqmp: Add reset-on-timeout for all boards and modify default timeout value
This patch adds reset-on-timeout to FPD WDT which will trigger an
interrupt to PMU when watchdog expiry happens and PMU takes the
necessary action. If this property is not enabled, reason will not be
known when watchdog expiry happens.
This patch also modifies the default timeout to 60 seconds. Reason is
that if u-boot enables WDT, it will set the timeout to 10 seconds and
this is not enough to boot till Linux and start the WDT application in
Linux. 60 seconds is the maximum safest value to boot till Linux and
start the WDT application.

Users need to change this timeout value to fit their needs.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:01 +01:00
Siva Durga Prasad Paladugu
e7c9de6617 arm64: zynqmp: Fix mmc node names to be in sync with kernel
This patches renames sd nodes in dts to be in line with
kernel. This patch also modifies the references for the same
in code.
It checks mmc first to have no time penalty for new DT node names based
on left-to-right expression evaluation.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
aedd54739f arm64: zynqmp: Remove power domain description
This part hasn't been pushed to mainline yet that's why remove it.
The patch can be reverted in future when this is pushed there.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-04-09 12:14:52 +02:00
Michal Simek
18a952ce7f arm64: zynqmp: Sync up license with mainline kernel
Mainline Linux kernel has adopted SPDX header license in a different
format then was used before. This patch is syncing it up.

Also update years in License text and remove Nathalie's email because it
is no longer valid.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:47 +02:00
Michal Simek
680e9976c9 arm64: zynqmp: Sync alignment with mainline
Sync pcie and lpd_dma nodes with mainline version.
Incorrect locations are causing diff in statistics that's why
synchronizations are needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:47 +02:00
Michal Simek
24124abe06 arm64: zynqmp: Add support for generic QSPI boot
This patch is enabling support for SPL QSPI boot.

First of all it is necessary to generate atf-spi.ub which is different
format than atf-uboot.ub (this can be made as legacy image too)

ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point
address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'`
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR
-e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin
atf-uboot.ub
./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR
-n "atf-for-qspi" -E -d bl31.bin atf-spi.ub

This patch is using this QSPI layout with offsets:
0 boot.bin
512k atf-ub
640k u-boot.bin
1280k u-boot.img

Which corresponding by writing these images(read from MMC)
mmcinfo
sf probe
load mmc 0 10000000 boot.bin
sf erase 0 +$filesize
sf write 10000000 0 $filesize
load mmc 0 10000000 atf-spi.ub
sf erase 0x80000 +$filesize
sf write 10000000 0x80000 $filesize
load mmc 0 10000000 u-boot.bin
sf erase 0xa0000 +$filesize
sf write 10000000 0xa0000 $filesize
load mmc 0 10000000 u-boot.img
sf erase 0x140000 +$filesize
sf write 10000000 0x140000 $filesize

For testing u-boot running in EL3 you can break atf-spi.ub like this:
sf probe
sf erase 0x80000 +4

Then u-boot.img is executed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-14 20:08:21 +01:00
Michal Simek
8a705a2d4d arm64: zynqmp: Add reference to pmu firmware node
This reference is needed for pinctrl driver where some signals can be
routed directly to platform management unit (PMU).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-14 20:08:21 +01:00
Anurag Kumar Vulisha
8861dcf2b9 arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB
This patch makes SMMU work by moving the iommus node under the dwc3 child
entry from parent node.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Michal Simek
a41bd46c2a arm64: zynqmp: Remove clock setting from dtsi
clock setting is handled via clk dtsi file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Anurag Kumar Vulisha
397a08ab92 arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3
This patch uncomments snps,quirk-frame-length-adjustment which has
the value to adjust the SOF/ITP generated from the controller.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Manish Narani
2ef98667b7 arm64: zynqmp: Add USB OTG interrupts support in dt
This patch adds OTG interrupt support in device tree. It will add
an extra interrupt line number dedicated to OTG events. This will
enable OTG interrupts to serve in DWC3 OTG driver.

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:16 +01:00
Manish Narani
f7346ef14c arm64: zynqmp: Enabled CCI support for USB
This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.

Also add address to unit name to avoid dtc warning

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
8e5a4e6f0e arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3
This patch adds support for reading silicon revision using zynqmp nvmem
driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
b0c55207bf arm64: zynqmp: Move nodes which have no reg property out of bus
Nodes without reg properties shouldn't be placed in amba node.
Move them out.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
795ebc0e64 arm64: zynqmp: dt: Add AMS node
The AMS includes an ADC as well as on-chip sensors that can be used to
sample external voltages and monitor on-die operating conditions, such as
temperature and supply voltage levels.

Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Manish Narani
5e3c90d238 arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon
This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
0aada397b5 arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset
This patch modifies the phy_zynqmp.c driver to use reset-controller
framework for asserting/de-asserting reset for High Speed modules.

Also fix documentation and dtsi.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Anurag Kumar Vulisha
98ad47bfab arm64: zynqmp: Add reset-controller support in serdes driver
This patch add the reset nodes in zynqmp.dtsi which are used by
reset-controller framework

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
3940bca4a8 arm64: zynqmp: Remove tx_termination_fix detection on silicon v1
Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Nava kishore Manne
0d87c4fd9b arm64: zynqmp: Add support for zynqmp nvmem firmware driver
Add support for zynqmp nvmem firmware driver.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:15 +01:00
Michal Simek
9c77cb73c7 arm64: zynqmp: Update device tree for pinmux
Added pin control support in device tree for zynqmp.

Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:10 +01:00
Jyotheeswar Reddy Mutthareddyvari
5f9b083cdb arm64: zynqmp: PM: Specify power domains for DP related nodes
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.

Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Naga Sureshkumar Relli
10f2a292b1 arm64: zynqmp: disable smmu
This patch disables the smmu and also removes the mmu-masters

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:09 +01:00
Nava kishore Manne
4d9d69856f arm64: zynqmp: rtc: Add calibration
This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Anurag Kumar Vulisha
110d06b2e3 arm64: zynqmp: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below

	SATA SMMU ID =  <TBU number>, 0011, 00, 00, AXI ID[1:0]
	Note: SATA in  ZynqMp uses TBU1 so TBU number = 0x1, so
	      SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]

Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values

 Read ID/ Write ID for Non-Data Port0 transfers = 0
 Read ID/ Write ID for Data Port0 transfers = 1
 Read ID/ Write ID for Non-Data Port1 transfers = 2
 Read ID/ Write ID for Data Port1 transfers = 3

Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Rob Herring
ec2b2d4c53 arm64: dts: xilinx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Michal Simek
0b33e0b156 arm64: zynqmp: Add missing gpio property to dtsi
All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Hyun Kwon
834ec8e9dd arm64: zynqmp: Update the GPU address size
The correct register size is 0x10000, otherwise
it overlaps with other register space.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Madhurkiran Harikrishnan
59206dd1e3 arm64: zynqmp: Add clock name for GPU
This patch will add names to the clocks used by GPU.

Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Nava kishore Manne
7689dce753 arm64: zynqmp: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00
Michal Simek
6db82e0956 arm64: zynqmp: Fix broken architected timer interrupt trigger
Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).

Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:09:08 +01:00