Commit graph

5 commits

Author SHA1 Message Date
Michal Simek
f7375aff95 ARM: zynq: Enable DM for CFI NOR flash
With multi defconfig NOR flash information about NOR should be taken from
DT that's why there is no reason to specify address and sizes via fixed
config.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:52:45 +02:00
Michal Simek
7c49a6d08e ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration
There is no real need to include full DT when only some nodes are enough to
use. It will save some space.

Retested with FSBL for initial SoC setup. SPL didn't work.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
df09969070 arm: zynq: Fix indentation for zynq-cse targets
Trivial DT style fixes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
7996fcca9d arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Siva Durga Prasad Paladugu
1c310aec67 arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:56 +02:00