Commit graph

21940 commits

Author SHA1 Message Date
Tom Rini
b487387226 Merge https://source.denx.de/u-boot/custodians/u-boot-pmic 2022-10-26 07:46:48 -04:00
Tom Rini
c2c485db45 Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- nuvoton: add expire function for generic reset (Jim)
- handle watchdogs during keyed autoboot (Rasmus)
- cyclic: Don't disable cylic function upon exceeding CPU time (Stefan)
- ulp wdog: Updates to support iMX93 and DM (Alice)
2022-10-26 07:45:55 -04:00
Michal Suchanek
0b9186277a power: fan53555: Fix missing newline in error message
Avoid concatenation with following message.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-26 11:47:25 +09:00
John Keeping
8edf7ac09f power: regulator: fix autoset error handling
If a regulator does not support .set_suspend_enable or
.set_suspend_value then ret is set to ENOSYS early in the function.

The most serious impact of this is that when no automatic setting of
voltage is needed then the final regulator_set_enable() is skipped
because ret has not been cleared.

It seems that the error handling for regulator_set_suspend_value() is
also wrong as if this succeeds then the normal boot-on checks are still
required, and again ENOSYS needs special treatment here.

Fixes: 11406b8f7e ("dm: regulator: support regulator more state")
Signed-off-by: John Keeping <john@metanate.com>
2022-10-26 11:47:12 +09:00
Tom Rini
f9d16f2c0d Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- Add s28hl512t, s28hl01gt (Takahiro)
- Rework s25hx_t_post_bfpt_fixup() (Takahiro)
2022-10-25 09:54:59 -04:00
Tom Rini
26bfb853ca Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc 2022-10-24 21:28:14 -04:00
Tom Rini
7d8ab3cd63 u-boot-imx-20221024
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916
 
 - for 2022.01
 - rework Kontron boards (mx6 and mx8)
 - fixes for Toradex
 - fixes (SPI, CAAM, )
 - sync DT with Linux
 - fixes for Gateworks GW7903 and GW7904 PMIC
 - Engicam i.Core MX8M Plus EDIMM2.2
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCY1aVgA8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76YlhwCfXTQJzJXruk6UKg1zbsimD3bsChUAoJFzB3yp
 zft+THzNdQTnfUGN9u+U
 =JHxW
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20221024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916

- for 2022.01
- rework Kontron boards (mx6 and mx8)
- fixes for Toradex
- fixes (SPI, CAAM, )
- sync DT with Linux
- fixes for Gateworks GW7903 and GW7904 PMIC
- Engicam i.Core MX8M Plus EDIMM2.2
2022-10-24 10:04:30 -04:00
Rasmus Villemoes
c9473b2c37 imx8m: fix reading of DDR4 MR registers [again]
Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.

However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].

I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.

So apply the fix from 290ffe5788 once again.

Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-24 11:34:33 +02:00
Alice Guo
5e112c7ca8 watchdog: ulp_wdog: add driver model for ulp watchdog driver
Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the
status of device node is "okay", initr_watchdog will be called and
finally calls ulp_wdt_probe() and ulp_wdt_start().

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Alice Guo
a7fd633501 watchdog: ulp_wdog: enable watchdog interrupt on imx93
The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the
source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset
needs to enable the watchdog interrupt.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Alice Guo
ef0ad9b07d watchdog: ulp_wdog: Update watchdog driver for imx93
The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the
timeout period exceeds 2 seconds, the value written to the TOVAL
register is larger than 16-bit can represent. Enabling watchdog
prescaler to solve this problem.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Ye Li
a79f2007d0 ulp_wdog: Update ulp wdog driver for 32bits command
To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-24 11:10:21 +02:00
Rasmus Villemoes
10107efedd sandbox: add SIGALRM-based watchdog device
In order to test that U-Boot actually maintains the watchdog device(s)
during long-running busy-loops, such as those where we wait for the
user to stop autoboot, we need a watchdog device that actually does
something during those loops; we cannot test that behaviour via the DM
test framework.

So introduce a relatively simple watchdog device which is simply based
on calling the host OS' alarm() function; that has the nice property
that a new call to alarm() simply sets a new deadline, and alarm(0)
cancels any existing alarm. These properties are precisely what we
need to implement start/reset/stop. We install our own handler so that
we get a known message printed if and when the watchdog fires, and by
just invoking that handler directly, we get expire_now for free.

The actual calls to the various OS functions (alarm, signal, raise)
need to be done in os.c, and since the driver code cannot get access
to the values of SIGALRM or SIG_DFL (that would require including a
host header, and that's only os.c which can do that), we cannot simply
do trivial wrappers for signal() and raise(), but instead create
specialized functions just for use by this driver.

Apart from enabling this driver for sandbox{,64}_defconfig, also
enable the wdt command which was useful for hand-testing this new
driver (especially with running u-boot under strace).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-10-24 11:10:21 +02:00
Rasmus Villemoes
2783670583 watchdog: introduce a u-boot,autostart property
This is a companion to u-boot,noautostart. If one has a single
watchdog device that one does want to have auto-started, but several
others that one doesn't, the only way currently is to set the
CONFIG_WATCHDOG_AUTOSTART and then use the opt-out for the majority.

The main motivation for this is to add an autostarted watchdog device
to the sandbox (to test a fix) without having to set AUTOSTART in
sandbox_defconfig and add the noautostart property to the existing
devices. But it's also nice for symmetry, and the logic in
init_watchdog_dev() becomes simpler to read because we avoid all the
negations.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-10-24 11:09:19 +02:00
Jim Liu
0ab55cb6f7 wdt: nuvoton: add expire function for generic reset
Add expire_now function for generic sysreset request

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-24 11:06:24 +02:00
Venkatesh Yadav Abbarapu
337af54a36 mmc: Fix static checker warnings
Correct pointer dereferencing check to be more consistent.

Eliminate the below smatch warning:
drivers/mmc/mmc.c:3118 mmc_init_device()
warn: variable dereferenced before check 'm' (see line 3116)

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:54 +09:00
John Keeping
7ff2f30b63 mmc: dwmmc: only clear handled interrupts
Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:

	mask = dwmci_readl(host, DWMCI_RINTSTS);

	// Hardware asserts DWMCI_INTMSK_DTO here

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);

	if (mask & DWMCI_INTMSK_DTO) {
		// Unreachable as DTO is cleared without being handled!
		return 0;
	}

Only clear interrupts that we have seen and are handling so that DTO is
not missed.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B)
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:41 +09:00
Yann Gautier
359c176de5 mmc: stm32_sdmmc2: manage vqmmc
The SDMMC IOs can be in an IO domain, that has to be enabled.
This is done by enabling vqmmc in the driver.
This has no impact on configurations not using an IO domain, the check
can then be executed on all platforms managing regulator, and the vqmmc
regulator enabled on all platforms having it in their DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:15 +09:00
Yann Gautier
27fbce4326 mmc: stm32_sdmmc2: protect against unsupported modes
The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:02:07 +09:00
Yann Gautier
be1872982e mmc: stm32_sdmmc2: add dual data rate support
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:59 +09:00
Kunihiko Hayashi
12fc8efe5a mmc: f_sdh30: Add support for F_SDH30_E51
Add Socionext F_SDH30_E51 IP support. The features of this IP includes
CMD/DAT line delay and force card insertion mode for non-removable cards.
And the IP needs to add some quirks.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2022-10-24 18:01:32 +09:00
Kunihiko Hayashi
2b0dd4174f mmc: sdhci: Add new quirks for SUPPORT_SINGLE
This patch defines a quirk to disable the block count
for single block transactions.

This is similar to Linux kernel commit d3fc5d71ac4d
("mmc: sdhci: add a quirk for single block transactions").

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:23 +09:00
Sergei Antonov
fc6b5d8260 mmc: ftsdc010: make command timeout 250 ms as in the comment
Get rid of discrepancy beween comment /* 250 ms */ and code
which shifts by 4 thus dividing by 16.
So change code to shift by 2 and make the timeout value 250 ms.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-24 18:01:07 +09:00
Takahiro Kuwano
e28d3ead72 mtd: spi-nor-core: Fix index value for SCCR dwords
Array index for SCCR 22th DWORD should be 21.

Fixes: bebdc23750 ("mtd: spi-nor: Parse SFDP SCCR Map")
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:52:16 +05:30
Takahiro Kuwano
7a4b6f8cf7 mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode
The flash's internal address mode is tracked by nor->add_mode_nbytes and
it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are
3- or 4-byte address mode by default, depending on model number. We need
to make sure that 4-byte address mode is used for multi-die package parts.

For single-die package parts (<=1Gb), registers can be accessed by 3-byte
address. Read, program, and erase use the 4B opcodes that always take
4-byte address regardless of flash's internal address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:38 +05:30
Takahiro Kuwano
f58e7b24fa mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes
Read/Write Any Register commands take 3- or 4- byte address depending on
flash's internal address mode. The nor->addr_width tracks number of
address bytes used in read/program/erase ops that can be 4
(with 4B opcodes) regardless of flash's internal address mode. The
nor->addr_mode_nbytes tracks flash's internal address mode so replace
nor->addr_width by that.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:26 +05:30
Takahiro Kuwano
4d60001fdf mtd: spi-nor-core: Track flash's internal address mode
The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:17 +05:30
Takahiro Kuwano
ee1c709cfd mtd: spi-nor-core: Default to addr_width of 3 for configurable widths
JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on
command."

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:50:04 +05:30
Takahiro Kuwano
de9e8378a8 mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs
Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt.
These devices have the same functionality as s28hs512t.

In spi-nor-core, use device ID byte to detect S28 family instead of
device name.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:43 +05:30
Takahiro Kuwano
f422c4bec7 mtd: spi-nor-core: Rename configuration macro for S28 support
Change configuration macro name to support all other devices in SEMPER S28
family.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:28 +05:30
Takahiro Kuwano
4bfeb00cc1 mtd: spi-nor-core: Rename s28hs512t prefix
Change prefix to support all other devices in SEMPER S28 family.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-23 10:44:15 +05:30
Alice Guo
71858454fe gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller
Add gpio driver for ADP5585 I/O Expander Controller. The ADP5585 is a 10
input/output port expander and can be used to increase the number of
I/Os available to a processor.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
2022-10-21 16:06:13 -04:00
Samuel Mendoza-Jonas
3b400e84ba net/ftgmac100: Add NC-SI mode support
Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.

NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio setup is
skipped in favour of the NC-SI phy.

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-21 16:04:39 -04:00
Samuel Mendoza-Jonas
09bd3d0b0a net: NC-SI setup and handling
Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-10-21 16:04:39 -04:00
Tom Rini
f60e6f6767 input: Remove legacy KEYBOARD option
There are no platforms that have not migrated to using DM_KEYBOARD,
remove the legacy option.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-21 13:47:56 -04:00
Tom Rini
9af4a0c8a6 core: Enable DM by default
There are no longer any platforms which do not enable DM, move this to a
def_bool y and remove the check in the Makefile.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-21 13:47:56 -04:00
Ye Li
eda25c11b8 crypto/fsl: fsl_rsa: Fix dcache issue in the driver
issue:
CAAM fails with key error when perform Modular Exponentiation
using PKHA Block in CAAM

Fix:
add flush and invalidate dcache for keys, signature
and output decrypted data processed by CAAM.

Fixes: 34276478f7 (DM: crypto/fsl - Add Freescale rsa DM driver)
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-10-21 11:54:13 +02:00
Fabio Estevam
1703a7c4c2 clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=y
The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the
QSPI clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
4ede070601 clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=y
The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the
ecspi clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
0d158e0181 clk-imx8mm: Move CLK_ENET_AXI to the non-SPL section
Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock
inside the non-SPL block to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Fabio Estevam
d63dc069ee clk-imx8mm: Only build PWM clocks in non-SPL code
PWM is not used inside SPL, so do not define the PWM clocks inside
SPL to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-21 11:54:13 +02:00
Ye Li
e0709aff27 mmc: fsl_esdhc: fix problem when using clk driver
Move init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-10-21 11:54:13 +02:00
Tom Rini
145a996592 Merge tag 'u-boot-rockchip-20221020' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- dts update and sync for rk356x, rk3288, rk3399 from Linux;
- Add rk3399 EAIDK-610 board support;
- Update for puma-rk3399 board;
- some fix and typo fix in different drivers;
2022-10-20 22:32:38 -04:00
Tom Rini
d843273a80 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2022-10-20 09:11:08 -04:00
Tom Rini
dc3cb0abf4 Clock patches for 2023.01
This contains various fixes (some long overdue) for the next release.
 -----BEGIN PGP SIGNATURE-----
 
 iQGTBAABCgB9FiEEkGEdW86NSNID6GAoPuiP7LShEG4FAmNQLrdfFIAAAAAALgAo
 aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldDkw
 NjExRDVCQ0U4RDQ4RDIwM0U4NjAyODNFRTg4RkVDQjRBMTEwNkUACgkQPuiP7LSh
 EG59kQf/WHyc0gXWxzI2nCjlq+ERL12rdswsy1N6rPVB++a6qCO8puFJWoMOYNa0
 deEMye5lYlhPFnfLLBLuMtpoeQW6R0dsNCkUeGuVfmwWDLW77tqb9LSg3nqD4bMg
 Fd+mlkFVmKa0WU5/uklojHLQGUEzvFsTVfMmpfOr7js2jsOYXW6DBSXuF1PogTRh
 YOJ9+OFq5giNtoSj339s807S/sEbaM46C72h0S+2iKKIED5FGy4Hi+mN7q8/GUDS
 TP1zt5xuaYwu6qo586y9/yNPbmmfHF+Liw35EZCairyEAjxevjLw6xJsFyZvtTxM
 11hKabfN//eSMTTB6Q4ugahRM3nELg==
 =H1Iz
 -----END PGP SIGNATURE-----

Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clk

Clock patches for 2023.01

This contains various fixes (some long overdue) for the next release.
2022-10-20 08:58:25 -04:00
Tom Rini
73ceadcd72 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Beside some rather unexciting sync of the DTs from the kernel tree, and
some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner
family, to support boards with the F1C200s (64MB DRAM) better. We will
get actual board support as soon as the DTs have passed the Linux review
process.
There is also support for the X96 Mate TV Box, featuring the H616 SoC and
a full 4GB of DRAM.
Also we found the secret to enable SPI booting on the H616 (pin PC5 must
be pulled to GND), so the SPI boot support patch is now good to go.

Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
X96 Mate and OrangePi Zero.
2022-10-20 08:58:05 -04:00
Heinrich Schuchardt
e77ef0bb74 k210: fix k210_pll_calc_config()
The k210 driver is selected by sandbox_defconfig.
Building the sandbox on 32bit systems fails with:

test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’:
include/linux/bitops.h:11:38: warning:
left shift count >= width of type [-Wshift-count-overflow]
   11 | #define BIT(nr)         (1UL << (nr))
      |                              ^~
test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’
   36 |                         error = abs((error - BIT(32))) >> 16;
      |                                              ^~~

Use the BIT_ULL() macro to create a u64 value.
Replace abs() by abs64() to get correct results on 32bit system
Apply the same for the unit test.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-10-20 15:22:30 +08:00
Patrick Delaunay
19fb40a5e7 clk: update clk_clean_rate_cache to use private clk struct
In clk_clean_rate_cache, clk->rate should update the private clock
struct, in particular when CCF is activated, to save the cached
rate value.

When clk_get_parent_rate is called, the cached information
is read from pclk->rate, with pclk = clk_get_parent(clk).

As the cached is read from private clk data, the update should
be done also on it.

Fixes: 6b7fd3128f ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid
Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-10-19 12:28:30 -04:00
Michal Suchanek
aa36a74f0f rockchip: clk: pll: Fix constant typo
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
2022-10-19 12:06:48 -04:00
Michal Suchanek
a1265cd580 clk: change return type of clk_get_parent_rate from long long to ulong
All functions getting and setting clock rate use ulong for rate, only
clk_get_parent_rate is an exception. Change the return value to match
other clock rate funcrions.

Most users directly assign the rate to unsigned long anyway, and the few
users that use u64 (not s64) multiply the rate so they may need the
extra bits for the result in their use case.

Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20220928103757.11870-1-msuchanek@suse.de
2022-10-19 12:06:41 -04:00