The environment is used to configure some additional boot features such as:
* extra boot arguments
* enable AVB (Android Verified Boot) verification
Right now, we cannot store it in eMMC:
Loading Environment from nowhere... OK
Fix it by enabling the appropriate options in the defconfig
Fixes: b749d5ecdc ("configs: meson64_android: define raw parts for bootloader")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231026-fix-saveenv-v1-1-6aa59be65481@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
A38x bootrom only searches 2 sectors when booting from eMMC,
irregardless of data or boot partition: 0 & 4096.
For eMMC boot partitions sector 0 is fine, but on data partition it
conflicts with MBR.
Change bubt command default to 4096 for eMMC data partition only, to
allow using an MBR partition table on the eMMC data partition while also
booting from it.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Disarm the error message forcing u-boot/spl image to be located at
sector 0 on eMMC data-partition and microSD.
Offset 0 makes sense on eMMC boot partitions only, data partition must
use 4096 to avoid conflicting with MBR.
Valid offsets when booting from microSD, reported by boot-rom v1.73:
BootROM: Bad header at offset 00000200
BootROM: Bad header at offset 00004400
BootROM: Bad header at offset 00200000
BootROM: Bad header at offset 00400000
BootROM: Bad header at offset 00600000
BootROM: Bad header at offset 00800000
BootROM: Bad header at offset 00A00000
BootROM: Bad header at offset 00C00000
BootROM: Bad header at offset 00E00000
BootROM: Bad header at offset 01000000
BootROM: Bad header at offset 01200000
BootROM: Bad header at offset 01400000
BootROM: Bad header at offset 01600000
BootROM: Bad header at offset 01800000
BootROM: Bad header at offset 01A00000
BootROM: Bad header at offset 01C00000
BootROM: Bad header at offset 01E00000
BootROM: Bad header at offset 02000000
BootROM: Bad header at offset 02200000
BootROM: Bad header at offset 02400000
BootROM: Bad header at offset 02600000
BootROM: Bad header at offset 02800000
BootROM: Bad header at offset 02A00000
BootROM: Bad header at offset 02C00000
BootROM: Bad header at offset 02E00000
Valid offsets when booting from eMMC:
BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000
Switching BootPartitions.
BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Extend Turris Mox board code to support CZ.NIC's RIPE Atlas Probe.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reformat and keep ncurses-dev needed for 'make menuconfig'
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
- Remove common.h in a number of places and make checkpatch.pl complain
about its use in all cases, allow the mbr command to handle 4 primary
partitions, fix an issue with the pstore command, fix a problem with
cli parsing of escape sequences, remove and ignore more files, allow
for the serial port to be flushed with every print (for debugging),
and add SCMI power domain support.
When debugging, one sometimes only gets partial output lines or
nothing at all from the last printf, because the uart has a largish
buffer, and the code after the printf() may cause the CPU to hang
before the uart IP has time to actually emit all the characters. That
can be very confusing, because one doesn't then know exactly where the
hang happens.
Introduce a config knob allowing one to wait for the uart fifo to
drain whenever a newline character is printed, roughly corresponding
to the effect of setvbuf(..., _IOLBF, ...) in ordinary C programs.
Since this uses IS_ENABLED() instead of cpp ifdef, we can remove the
ifdef around the _serial_flush() definition - if neither
CONSOLE_FLUSH_SUPPORT or CONSOLE_FLUSH_ON_NEWLINE are enabled, the
compiler elides _serial_flush(), but it won't warn about it being
unused.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
This ut has tests for the SCMI power domain protocol as well as DM
interfaces for power domain devices.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
SCMI power domain management protocol is supported on sandbox
for test purpose. Add fake agent interfaces and associated
power domain devices.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
In this patch, added are helper functions to directly manipulate
SCMI power domain management protocol. DM compliant power domain
driver will be implemented on top of those interfaces in a succeeding
patch.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Current code allows up to 3 MBR partitions without extended one.
If more than 3 partitions are required, then extended partition(s)
must be used.
This commit allows up to 4 primary MBR partitions without the
need for extended partition.
Add mbr test unit. In order to run the test manually, mmc6.img file
of size 12 MiB or greater is required in the same directory as u-boot.
Test also runs automatically via ./test/py/test.py tool.
Running mbr test is only supported in sandbox mode.
Signed-off-by: Alex Gendin <agendin@matrox.com>
[ And due to some further changes for testing ]
Signed-off-by: Simon Glass <sjg@chromium.org>
u-boot adds reserve-memory node, if it's missing, with following
properties:
```
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
}
```
But with these default address-cells and size-cells values, pstore
isn't working on A64. Root node for A64 defines 'address-cells' and
'size-cells' as 1.
dtc complains if reserved-memory has different address-cells and
size-cells.
```
Warning (ranges_format): /reserved-memory:ranges: empty "ranges"
property but its #address-cells (2) differs from / (1)
```
This patch takes into account address-cells and size-cells of the root
node and uses them as values for new reserved-memory node.
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
make rock5b-rk3588_defconfig
make
git status
before
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
Untracked files:
(use "git add <file>..." to include in what will be committed)
include/autoconf.mk
include/autoconf.mk.dep
include/config.h
mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
mkimage-in-simple-bin-spi.mkimage-u-boot-spl
mkimage-in-simple-bin.mkimage-rockchip-tpl
mkimage-in-simple-bin.mkimage-u-boot-spl
simple-bin-spi.map
simple-bin.fit.fit
simple-bin.fit.itb
simple-bin.map
tools/generated/
after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
nothing to commit, working tree clean
Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
make rock5b-rk3588_defconfig
make
make clean
git status
before
~~~~~~~
On branch master
Your branch is up to date with 'origin/master'.
Untracked files:
(use "git add <file>..." to include in what will be committed)
include/autoconf.mk
include/autoconf.mk.dep
include/config.h
mkimage-in-simple-bin-spi.mkimage-rockchip-tpl
mkimage-in-simple-bin-spi.mkimage-u-boot-spl
mkimage-in-simple-bin.mkimage-rockchip-tpl
mkimage-in-simple-bin.mkimage-u-boot-spl
simple-bin.fit.fit
simple-bin.fit.itb
after
~~~~~~~
On branch master
Your branch is ahead of 'origin/master' by 1 commit.
(use "git push" to publish your local commits)
nothing to commit, working tree clean
Signed-off-by: John Clark <inindev@gmail.com>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Michal Simek <michal.simek@amd.com>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
These files references a number of types that are defined in
<linux/types.h> (and so forth), so include it here rather than rely on
indirect inclusion.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At this point in time we should not add common.h to any new files, so
make checkpatch.pl complain.
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Unexpected 'Esc' key presses are accumulated internally, even if it is
already clear that the current escape sequence is invalid. This results
in weird behaviour. For example, the next character after 'Esc' key
simply disappears from input and 'Unknown command' is printed
after 'Enter'.
This commit fixes some issues with extra 'Esc' keys entered by user:
1. Sequence <Esc><Esc><Enter> right after autoboot stop gives:
=>
nknown command 'ry 'help'
=>
2. Sequence <Esc><p><r><i><Enter> gives:
=> ri
Unknown command 'ri' - try 'help'
=>
3. Extra 'Esc' key presses break backspace functionality.
Signed-off-by: Yurii Monakov <monakov.y@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus;
- clk driver fix for rk3568 and rk3588;
- rkmtd cmd support for rockchip nand device;
- dts update and sync from linux;
Enable rkmtd command for testing with sandbox_defconfig
and sandbox64_defconfig.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add documention for Rockchip rkmtd virtual block device.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add Rockchip rkmtd test:
Create/attach/detach RKMTD device.
Send/read data with Rockchip boot block header.
Test that reusing the same label should work.
Basic test of 'rkmtd' commands.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The command rkmtd creates a virtual block device to transfer
Rockchip boot block data to and from NAND with block orientated
tools like "ums" and "rockusb".
It uses the Rockchip MTD driver to scan for boot blocks and copies
data from the first block in a GPT formated virtual disk.
Data must be written in U-boot "idbloader.img" format and start at
partition "loader1" offset 64. The data header is parsed
for length and offset. When the last sector is received
it erases up to 5 erase blocks on NAND and writes bootblocks
in a pattern depending on the NAND ID. Data is then verified.
When a block turns out bad the block header is discarded.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently bounce buffer support is enabled for all block devices
when available. Add a flag to blk_desc to enable only on demand.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add rkmtd class and drivers to create a virtual block device
to transfer Rockchip boot block data to and from NAND with
block orientated tools like "ums" and "rockusb".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Prepare a rkmtd UCLASS in use for writing Rockchip boot blocks
in combination with existing userspace tools and rockusb command.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On Rockchip SoCs the first boot stages are written on NAND
with help of manufacturer software that uses a different format
then the MTD framework. Skip the automatic BBT scan with the
NAND_SKIP_BBTSCAN option to be able to pass the driver probe
function and to let the original data unchanged.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C.
Features tested on a Orange Pi 5 Plus 4GB v1.2:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.
Features tested on a Orange Pi 5 4GB v1.2:
- SD-card boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for XMC XM25QU128C (128M-bit) Serial Flash memory. Used on
the Xunlong Orange Pi 3B, 5 and 5 Plus boards.
Datasheet:
https://www.xmcwh.com/uploads/806/XM25QU128C_Ver2.0.pdf
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
[jonas@kwiboo.se: update commit message]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].
Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic driver can be updated to include support for the
rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3
compatible until final node is merged in linux maintainer tree.
[1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collabora.com/
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable support for PCIe SATA cards and the on-board SATA controller.
This also revert use of CONFIG_PCI_INIT_R in order to speed up boot from
eMMC or SD-cards. Standard boot will initialize pci after faster boot
media have been enumerated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable Kconfig options for the two USB 2.0 ports and bottom USB 3.0 port
on ROCK 5 Model A.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This brings in more colours, e.g. ORANGE needed for the QuartzPro64 DT.
Linux commits:
472d7b9e8141 ("dt-bindings: leds: Expand LED_COLOR_ID definitions")
Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
It's normal to have no SATA drive attached to the controller, so return a
successful status when there is no block device found after probing.
Note: this patch depends on the previous patch
https://patchwork.ozlabs.org/project/uboot/patch/20230917230649.30357-1-mibodhi@gmail.com/
Resend the right patch.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
