Commit graph

22 commits

Author SHA1 Message Date
Andre Schwarz
846f1574dd fix system config overwrite @ MPC834x and MPC8313
During 83xx setup the "System I/O configuration register high" gets
overwritten with user defined value if CFG_SICRH is defined.

Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH
must keep their reset value regardless of configuration.

On my board (using RGMII) those bits are set after reset - yet it's
unclear where they come from.

The patch keeps both bits on MPC834x and MPC8313.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-25 17:04:28 -05:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Michael Barkowski
5bbeea86eb mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Dave Liu
a8cb43a89b mpc83xx: Fix the fatal conflict of merge
The commit 9e89647889
will cause the mpc8315erdb board can't boot up.

The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-17 11:01:52 -06:00
Kim Phillips
9e89647889 mpc83xx: add support for more system clock performance controls
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).

Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 12:32:39 -06:00
Dave Liu
b05884efa6 mpc83xx: Add config of eTSEC emergency priority in SPCR
The TSEC emergency priority definition of 831x/837x
is different than the definition of 834x in SPCR register.

Add the other config of TSEC emergency priority into
cpu_init.c

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 12:00:49 -06:00
Dave Liu
19580e660c mpc83xx: Add the support of MPC837xEMDS board
The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08 09:55:39 -06:00
Dave Liu
9be39a67c9 mpc83xx: Add support for the display of reset status
83xx processor family has many reset sources, such as
power on reset, software hard reset, software soft reset,
JTAG, bus monitor, software watchdog, check stop reset,
external hard reset, external software reset.
sometimes, to figure out the fault of system, we need to
know the cause of reset early before the prompt of
u-boot present.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:03 -05:00
Timur Tabi
df33f6b4d6 Update SCCR programming in cpu_init_f() to support all 83xx processors
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors.  The code to update some bitfields was
compiled only on some processors.  Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:03 -05:00
Kumar Gala
4feab4de7b mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02 14:08:26 -06:00
Dave Liu
24c3aca3f1 mpc83xx: Add support for the MPC832XEMDS board
This patch supports DUART, ETH3/4 and PCI etc.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
Dave Liu
e080313c32 mpc83xx: streamline the 83xx immr head file
For better format and style, I streamlined the 83xx head files,
including immap_83xx.h and mpc83xx.h. In the old head files, 1)
duplicated macro definition appear in the both files; 2) the structure
of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
macro definition put inside the each structure. So, I cleaned up the
structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
moved the macro definition to mpc83xx.h, Just like MPC8260.

CHANGELOG

*streamline the 83xx immr head file

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
Timur Tabi
e857a5bdb3 mpc83xx: Miscellaneous code style fixes
Implement various code style fixes and similar changes.

Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-28 23:34:30 -06:00
Timur Tabi
d239d74b1c mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.

Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-03 19:42:23 -06:00
Dave Liu
7737d5c658 mpc83xx: add QE ethernet support
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
2006-11-03 19:42:21 -06:00
Timur Tabi
2ad6b513b3 mpc83xx: Add support for the MPC8349E-mITX
PREREQUISITE PATCHES:

* This patch can only be applied after the following patches have been applied:

  1) DNX#2006090742000024 "Add support for multiple I2C buses"
  2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
  3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
  4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
  5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"

CHANGELOG:

* Add support for the Freescale MPC8349E-mITX reference design platform.
  The second TSEC (Vitesse 7385 switch) is not supported at this time.

Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-03 19:42:20 -06:00
Wolfgang Denk
d87080b721 GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
Kumar Gala
c99f384dce Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
Patch by Kumar Gala, 25 Jan 2006
2006-01-25 16:12:46 -06:00
Kumar Gala
a15b44dbfa Allow config of GPIO direction & data registers at boot on 83xx
Patch by Kumar Gala, 11 Jan 2006
2006-01-11 11:21:14 -06:00
Kumar Gala
9260a56151 Make System IO Config Registers board configurable on MPC83xx
Patch by Kumar Gala, 11 Jan 2006
2006-01-11 11:12:57 -06:00
Jon Loeliger
de1d0a6995 Fix style issues primarily in 85xx and 83xx boards.
- C++ comments
    - Trailing white space
    - Indentation not by TAB
    - Excessive amount of empty lines
    - Trailing empty lines
2005-08-01 13:20:47 -05:00
Eran Liberty
f046ccd15c * Patch by Eran Liberty
Add support for the Freescale MPC8349ADS board.
2005-07-28 10:08:46 -05:00