This patch implements the reading functionality for the generic I2C
EEPROM driver, which was just a non-functional stub until now.
Since the page size will be of importance for the writing support, we
add suitable members to the private data structure to keep track of it.
Compatibility strings for a range of at24c* chips are added.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a driver which uses of-platdata to obtain its platform data. This can
be used to test the feature in sandbox. It displays the contents of its
platform data.
Signed-off-by: Simon Glass <sjg@chromium.org>
The cros-ec keyboard is always a child of the cros-ec node. Rather than
searching the device tree, looking at the children. Remove the compat string
which is now unused.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current reset API implements a method to reset the entire system.
In the near future, I'd like to introduce code that implements the device
tree reset bindings; i.e. the equivalent of the Linux kernel's reset API.
This controls resets to individual HW blocks or external chips with reset
signals. It doesn't make sense to merge the two APIs into one since they
have different semantic purposes. Resolve the naming conflict by renaming
the existing reset API to sysreset instead, so the new reset API can be
called just reset.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly code which prevents it being ported to other architectures.
This patch adds callback functions and moves those to arch/x86/
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.
Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.
Move these options to Kconfig and tidy up board configuration:
CONFIG_FIT
CONFIG_OF_BOARD_SETUP
CONFIG_OF_SYSTEM_SETUP
CONFIG_FIT_SIGNATURE
CONFIG_FIT_BEST_MATCH
CONFIG_FIT_VERBOSE
CONFIG_OF_STDOUT_VIA_ALIAS
CONFIG_RSA
Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.
Note: Masahiro's moveconfig.py script is amazing.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some devices need special sequences to be used when starting up. Add a
uclass for this. Drivers can be added to provide specific features as
needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <trini@konsulko.com>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Building with gcc-5.2 raises this warning:
drivers/misc/cros_ec_sandbox.c: In function cros_ec_sandbox_packet:
drivers/misc/cros_ec_sandbox.c:483:5: warning: len may be used uninitialized in this function [-Wmaybe-uninitialized]
if (len < 0)
^
If the function process_cmd() is called with
req_hdr->command == EC_CMD_ENTERING_MODE, the value of len will be
returned uninitialized.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In preparation for converting the cros_ec keyboard driver to driver model,
adjust the cros_ec functions it will use to use a normal struct udevice.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change ioremap() to map_physmem(), as it is more used in u-boot.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For current U-Boot to initialize status LEDs via status_led_init(), it
is required to have both CONFIG_STATUS_LED and STATUS_LED_BOOT defined.
This may be a particular concern with GPIO LEDs, where __led_init() is
required to correctly set up the GPIO (gpio_request and
gpio_direction_output). Without STATUS_LED_BOOT the initialization isn't
called, which could leave the user with a non-functional "led" command -
due to the fact that the LED routines in gpio_led.c use gpio_set_value()
just fine, but the GPIO never got set up properly in the first place.
I think having CONFIG_STATUS_LED is sufficient to justify a
corresponding call to status_led_init(), even with no STATUS_LED_BOOT
defined. To do so, common/board_r.c needs call that routine, so it now
is exposed via status_led.h.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
[trini: Add dummy __led_init to pca9551_led.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
For boards that support LEDs driven via GPIO (CONFIG_GPIO_LED),
it may be useful to have some generic stubs (wrapper functions)
for the "colored" LEDs.
This allows defining STATUS_LED_* values directly to GPIO numbers,
e.g.: #define STATUS_LED_GREEN 248 /* = PH24 */
To keep those optional, it's probably best to introduce an additional
configuration setting. I've chosen CONFIG_GPIO_LED_STUBS for that.
Placing the code in drivers/misc/gpio_led.c also ensures that it
automatically depends on CONFIG_GPIO_LED too.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Implement a Miscellaneous uclass with generic read or
write operations. This class is used only for those
do not fit other more general classes.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
Currently 'reset' only works with the test device tree. When run without a
device tree, or with the normal device tree, the following error is
displayed:
Reset not supported on this platform
Fix the driver and the standard device tree to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is a hole in shadow registers address map of size 0x100
between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
we should account for this hole in address space.
Similar hole exists between bank 14 and bank 15 of size
0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
Note: iMX6SL has only 0-7 banks and there is no hole.
Note: iMX6UL doesn't have this one.
When reading, we use register offset, so need to account for holes
to get the correct address.
When writing, we use bank/word index, there is no need to account
for holes, always use bank/word index from fuse map.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
* Ocotp of i.MX7D has different operation rule.
This patch is to add support for i.MX7D ocotp.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk()
for the purpose or restoring it back later, the value is not shifted by the
HBUS divider offset in that register. This is not a problem, since the shift
is zero on all MXS hardware. Add the shift anyway, for completeness and in
case FSL ever decides to re-use this driver on future designs.
Signed-off-by: Chris Smith <chris@zxdesign.info>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.
For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.
Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Append "debug server FW" in error message to make more informative.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add an api to enable and configure the integrated keyboard controller
on SMSC LPC47m superio chipset. It also adds several macros to help
future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu. Use hierarchic menu for each category.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add a driver to support the special LDO access used by spring. This is a
custom method in the cros_ec protocol - it does not use an I2C
pass-through.
There are two implementation choices:
1. Write a special LDO driver which can talk across the EC. Duplicate all
the logic from TPS65090 for retrying when the LDO fails to come up.
2. Write a special I2C bus driver which pretends to be a TPS65090 and
transfers reads and writes using the LDO message.
Either is distasteful. The latter method is chosen since it results in less
code duplication and a fairly simple (30-line) implementation of the core
logic.
The crosec 'ldo' subcommand could be removed (since i2c md/mw will work
instead) but is retained as a convenience.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This
currently uses a copy of the I2C command code and a special 'crosec'
sub-command.
With driver model we can define an I2C bus which tunnels through to the EC,
and use the normal 'i2c' command to access it. This simplifies the code and
removes some duplication.
Add an I2C driver which tunnels through to the EC. Adjust the EC code to
support binding child devices so that it can be set up. Adjust the existing
I2C xfer function to fit driver model better.
For now the old code remains to allow things to still work. It will be
removed in a later patch once the new flow is fully enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only 2 frequencies are supported. The current driver implementation does
not always use the 2 last configured blink frequencies. This patch
fixes this problem. So that the last two entered frequencies are
active.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Move sandbox over to use the reset uclass for reset, instead of a direct
call to do_reset(). This allows us to add tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add drivers for sandbox. One can only perform a warm reset (which does
nothing). The other can perform a cold reset or a power reset (the
latter will quit U-Boot). These can be used for testing the reset uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new reset_walk_halt() function to cause a reset and then halt on
failure. The reset_walk() function returns an error code.
This is needed for testing since otherwise U-Boot will halt in the middle
of a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds a driver for the PCA9551 LED controller.
Originated-by: Timo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
With several chips using the SPI protocol it seems better to put the single
duplex functionality in the EC rather than the SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
For starting a Linux console on the superio serial port under
interrupt mode, the IRQ number must be configured.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This patch extends the U-Boot "led" command to support automatic blinking
by setting a blink frequency in milliseconds. Additionally the number of
supported LEDs is increased to 6 (0...5).
This will be used by the PCA9551 LED driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:
MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.
For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.
Signed-off-by: Simon Glass <sjg@chromium.org>
This command is supposed to reinit the device. At present with driver
model is does nothing. Implement this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Security Monitor is the SOC’s central reporting point for
security-relevant events such as the success or failure of boot
software validation and the detection of potential security compromises.
The API's for transition of Security states have been added
which will be used in case of SECURE BOOT.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Since both I2C and SPI are converted to Kconfig, we can convert cros_ec
to Kconfig for these buses.
LPC will need to wait until driver mode PCI is available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
I2C is now deprecated on ARM platforms and there are no devices that use it
with the v3 protocol. We can't require v3 support if we want to support I2C.
Adjust the error handling to suit.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.
However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.
Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.
Signed-off-by: Simon Glass <sjg@chromium.org>
drivers/misc/i2c_eeprom.c fails to build unless CONFIG_FIT_SIGNATURE
is defined.
CC drivers/misc/i2c_eeprom.o
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:15:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:15:10: note: each undeclared identifier
is reported only once for each function it appears in
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_write':
drivers/misc/i2c_eeprom.c:21:10: error: 'ENODEV' undeclared
(first use in this function)
drivers/misc/i2c_eeprom.c:22:1: warning: control reaches end of
non-void function [-Wreturn-type]
drivers/misc/i2c_eeprom.c: In function 'i2c_eeprom_read':
drivers/misc/i2c_eeprom.c:16:1: warning: control reaches end of
non-void function [-Wreturn-type]
make[2]: *** [drivers/misc/i2c_eeprom.o] Error 1
make[1]: *** [drivers/misc] Error 2
make: *** [drivers] Error 2
By the way, Sandbox (enabling CONFIG_FIT_SIGNATURE) is luckily
working depending on it.
Sandbox includes include/asm-generic/errno.h
from include/errno.h
from include/u-boot/rsa-checksum.h
from include/image.h
from include/common.h
from drivers/misc/i2c_eeprom.c
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Leave the OCOTP turned on, so that we subsequent access do not fail.
After enabling the thermal driver on a mx6sxsabresd board:
U-Boot 2015.01-rc1-18267-g99d4189-dirty (Nov 24 2014 - 12:59:01)
CPU: Freescale i.MX6SX rev1.0 at 792 MHz
CPU: Temperature 48 C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller
In: serial
Out: serial
Err: serial
Net:
(hang)
As the thermal driver accesses the ocotp registers, its clock will be disabled
afterwards.
Then when the MAC address is read (also from ocotp registers) it will cause a
hang.
Do not disable the ocotp clock to prevent this problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
A previous operation may have set the error flag, which must be cleared
before a new write operation can be issued.
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
The write operation may fail when trying to write to a locked area. In
this case the ERROR bit is set in the CTRL register. Check for that
condition and return an error.
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
The code may goto 'fail' upon error with 'ret' variable set to an error
code, but this variable was being overwritten by a final preparation
function to restore the HCLK, so success was (in general) returned even
after an error was hit previously.
With this change, the function may now return success even if the final
preparation function fails, but it's probably enough to print a message
because (if successful) the real programming of the fuses has already
completed.
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does. This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.
Many of references of those macros must be fixed to suppress warnings.
We have two options:
- Use min, max, min3, max3 only when the arguments have the same type
(or add casts to the arguments)
- Use min_t/max_t instead with the appropriate type for the first
argument
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
This fixes this cppcheck report:
[drivers/misc/cros_ec.c:704]: (error) Uninitialized variable: req
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Denk <wd@denx.de>
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.
For example,
foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Adjust this driver to use driver model and move smdk5420 boards over to
use it.
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the sandbox cros_ec emulation driver to work with driver model, and
switch over to driver model for sandbox cros_ec.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add support for driver model if enabled. This involves minimal changes
to the code, mostly just plumbing around the edges.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This would be useful to start moving various config options.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
