Commit graph

122 commits

Author SHA1 Message Date
Dave Liu
bcae52a681 mpc83xx: remove the unused CPM's stuff
The MPC83xx family never have CPM block, so remove it from 83xx.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-04-25 09:34:21 -05:00
Kim Phillips
78e4882988 lib_ppc: Revert "Make MPC83xx one step closer to full relocation."
This reverts commit 70431e8a73 which has
proven problematic getting right from the start at least on 83xx and
4xx.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-04-25 00:13:12 +02:00
Lee Nipper
3f9c542d3d mpc83xx: Update DIMM data bus width test to support 40-bit width
32-bit wide ECC memory modules report 40-bit width.
Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'.

Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-04-11 17:46:18 -05:00
Joakim Tjernlund
70431e8a73 Make MPC83xx one step closer to full relocation.
Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx
and use GOT relative reference.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 18:51:54 -05:00
Kim Phillips
e5c4ade4db mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
in the spirit of commit 1ced121600,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display.  Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler.  Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 16:01:06 -05:00
Kim Phillips
81fd52c6c8 mpc83xx: display ddr frequency in board_add_ram_info banner
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 14:32:09 -05:00
Kim Phillips
35cf155c5e mpc83xx: unreinvent mem_clk
delete ddr_clk and use mem_clk instead.  Rename other ddr_*_clk to
mem_*_clk for consistency's sake.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 14:32:07 -05:00
Anton Vorontsov
7fa9cbb00d mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups
device_type = "soc" is being deprecated, newer device trees will use
"fsl,soc" and/or "fsl,immr" for the soc nodes.

This patch also adds clock-frequency property for soc nodes (the same
value as bus-frequency).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:48 -05:00
Anton Vorontsov
453316a2a1 83xx: serdes setup routines
This patch adds few routines to configure serdes on 837x targets.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
a796cdf9c3 83xx: split COBJS onto separate lines
..plus get rid of some #ifdefs in the .c files.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:44 -05:00
Michael Barkowski
5bbeea86eb mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Wolfgang Denk
e7670f6c1e PPC: Use r2 instead of r29 as global data pointer
R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.

Use r2 instead.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-02-14 22:43:22 +01:00
Rafal Jaworowski
f57d7d364c ppc: Refactor cache routines, so there is only one common set.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-02-14 22:00:41 +01:00
Kumar Gala
69018ce2e0 QE: Move FDT support into a common file
Move the flat device tree setup for QE related devices into
a common file shared between 83xx & 85xx platforms that have QE's.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-12 00:36:21 +01:00
Dave Liu
a8cb43a89b mpc83xx: Fix the fatal conflict of merge
The commit 9e89647889
will cause the mpc8315erdb board can't boot up.

The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-17 11:01:52 -06:00
Kim Phillips
9e89647889 mpc83xx: add support for more system clock performance controls
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).

Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 12:32:39 -06:00
Dave Liu
b05884efa6 mpc83xx: Add config of eTSEC emergency priority in SPCR
The TSEC emergency priority definition of 831x/837x
is different than the definition of 834x in SPCR register.

Add the other config of TSEC emergency priority into
cpu_init.c

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 12:00:49 -06:00
Wolfgang Denk
64134f0112 Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections
With recent toolchain versions, some boards would not build because
or errors like this one (here for ocotea board when building with
ELDK 4.2 beta):
ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab]

For many boards, the .bss section is big enough that it wraps around
at the end of the address space (0xFFFFFFFF), so the problem will not
be visible unless you use a 64 bit tool chain for development. On
some boards however, changes to the code size (due to different
optimizations) we bail out with section overlaps like above.

The fix is to add the NOLOAD attribute to the .bss and .sbss
sections, telling the linker that .bss does not consume any space in
the image.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-12 20:31:39 +01:00
Heiko Schocher
f6db945649 Fixed syntax error in function init_e300_core() of mpc83xx/start.S if
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
2008-01-12 00:43:59 +01:00
Dave Liu
061aad4d32 mpc83xx: Fix the bug of 266MHz data rate DDR
The DDR doesn't work on the 266MHz data rate,
the patch fix the bug.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10 21:24:11 -06:00
Anton Vorontsov
b3d2cde7a3 mpc83xx: add "fsl, qe" compatible fixups
New device trees will use "fsl,qe" compatible properties.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10 20:52:47 -06:00
Kim Phillips
5b8bc606c6 mpc83xx: convert to using do_fixup_*()
convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08 09:56:42 -06:00
Joakim Tjernlund
ccf21c311e Add support CONFIG_UEC_ETH3 in MPC83xx
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2008-01-08 09:55:41 -06:00
Dave Liu
19580e660c mpc83xx: Add the support of MPC837xEMDS board
The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08 09:55:39 -06:00
Dave Liu
555da61702 mpc83xx: Add the support of MPC8315E SoC
The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08 09:55:39 -06:00
Dave Liu
03051c3d35 mpc83xx: Add the support of MPC837x SoC
The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08 09:55:39 -06:00
Kumar Gala
246d4ae6bc Convert boards that set memory node to use fdt_fixup_memory()
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 20:51:25 -05:00
Kumar Gala
8d04f02f62 Update libfdt from device tree compiler (dtc)
Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from
the device tree compiler (dtc) project.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-11-21 14:04:05 -06:00
Grant Likely
928fe33b24 Revert "Correct fixup relocation for mpc83xx"
This reverts commit 057004f4a4.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-11-15 08:31:17 -07:00
Kim Phillips
4cc1cd5941 mpc83xx: fix typo in DDR2 programming
introduced in the implement board_add_ram_info patch as I was cleaning out the
magic numbers.  sorry.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-17 09:30:00 -05:00
Kim Phillips
bbea46f76f mpc83xx: implement board_add_ram_info
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:

DRAM:  256 MB (DDR1, 64-bit, ECC on)

and for boards with SDRAM on the local bus, a line such as this is
added:

SDRAM: 64 MB (local bus)

also replaced some magic numbers with their equivalent define names.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-16 23:12:24 -05:00
Kim Phillips
3fde9e8b22 mpc83xx: migrate remaining freescale boards to libfdt
this adds libfdt support code for the freescale
mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx,
and gp boards.

Boards remain compatible with OF_FLAT_TREE.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-15 22:36:33 -05:00
Kim Phillips
6a16e0dfcc mpc83xx: move common /memory node update mechanism to cpu.c
also adds common prototypes to include/common.h.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-15 22:36:33 -05:00
Kim Phillips
8f9e0e9f33 mpc83xx: remaining 8360 libfdt fixes
PCI clocks and QE frequencies weren't being updated, and the core clock
was being updated incorrectly.  This patch also adds a /memory node if
it doesn't already exist prior to update.

plus some cosmetic trimming to single line comments.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-15 22:36:33 -05:00
Kim Phillips
f4b2ac5ed9 mpc83xx: fix UEC2->1 typo in libfdt setup code
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-15 22:36:33 -05:00
Dave Liu
49bb59912d mpc83xx: Suppress the warning 'burstlen'
suppress the warning 'burstlen' of spd_sdram.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-08-10 22:00:52 +02:00
Dave Liu
daab8c67d2 mpc83xx: Consolidate the ECC support of 83xx
Remove the duplicated source code of ecc command on the <board>.c,
for reused, move these code to cpu/mpc83xx directory.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:13:11 -05:00
Dave Liu
036575c544 mpc83xx: Correct the burst length for DDR2 with 32 bits
The burst length should be 4 for DDR2 with 32 bits bus

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-08-10 01:12:40 -05:00
Kim Phillips
343d91009d mpc83xx: fixup generic pci for libfdt
add libfdt support to the generic 83xx pci code

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:25 -05:00
Kim Phillips
f57ac7a7b3 mpc83xx: fix 8360 and cpu functions to update fdt being passed
..and not the global fdt. Rename local fdt vars to blob so as not to
be confused with the global var with the same three-letter name.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:25 -05:00
Jerry Van Baren
8be404459a mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabled
Several node strings were not correct (trailing slashes and properties
  in the strings)
Added setting of the timebase-frequency.
Improved error messages and use debug() instead of printf().

Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:25 -05:00
Jerry Van Baren
26d02c9bba mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path().
The new name matches more closely the kernel's name, which is also
a much better description.

These are the mpc83xx changes made necessary by the function name change.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:03 -05:00
Dave Liu
9be39a67c9 mpc83xx: Add support for the display of reset status
83xx processor family has many reset sources, such as
power on reset, software hard reset, software soft reset,
JTAG, bus monitor, software watchdog, check stop reset,
external hard reset, external software reset.
sometimes, to figure out the fault of system, we need to
know the cause of reset early before the prompt of
u-boot present.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:03 -05:00
Timur Tabi
df33f6b4d6 Update SCCR programming in cpu_init_f() to support all 83xx processors
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors.  The code to update some bitfields was
compiled only on some processors.  Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:03 -05:00
Lee Nipper
1ded0242e4 mpc83xx: Add support for 8360 silicon revision 2.1
This change adds 8360 silicon revision 2.1 support to u-boot.

Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10 01:12:02 -05:00
Jon Loeliger
4431283c7e cpu/m*: Remove obsolete references to CONFIG_COMMANDS
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-09 19:06:00 -05:00
Grant Likely
057004f4a4 Correct fixup relocation for mpc83xx
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-07-04 01:08:40 +02:00
Grant Likely
416a0b6d40 Consolidate mpc83xx linker scripts
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-07-04 01:05:12 +02:00
Jon Loeliger
f48070fe5f cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.

All transformations are of the form:
Before:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
    #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-04 00:23:18 +02:00
Wolfgang Denk
98c440bee6 Merge with /home/wd/git/u-boot/custodian/u-boot-testing 2007-07-03 15:07:56 +02:00