Commit graph

180 commits

Author SHA1 Message Date
Stefan Roese
499e7831e1 ppc4xx: Change Canyonlands to support booting from 2k page NAND devices
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:30:49 +02:00
Jason Wessel
3d36be0300 Remove all the search paths from the .lds files.
The cross compiler is responsible for providing the correct libraries
and the logic to find the linking libraries.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2008-04-17 23:57:32 -07:00
Stefan Roese
1c2926abdd ppc4xx: Canyonlands: Init SATA/PCIe port correctly
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
correctly configures the SATA/PCIe PHY for SATA usage when this jumper
is installed.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-02 08:39:33 +02:00
Stefan Roese
cc8e839abc ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revision
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA
interface. This usage can be configured with the jumper J6. This patch
displays the current configuration upon bootup and changes the PCIe
init loop, to only initialize the availabel PCIe slots.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-28 14:09:04 +01:00
Stefan Roese
c664bf8c3c ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 10:09:05 +01:00
Stefan Roese
d56a3ce179 ppc4xx: Correctly pass phyiscal FLASH base address into dtb
The routine ft_board_setup() configures the EBC NOR mappings for the
Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from
0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS
problem, we need to pass the corrected address here too.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
4c9e855734 ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
41712b4e8c ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board
This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Stefan Roese
71665ebf88 ppc4xx: Add Canyonlands NAND booting support
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.

This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.

Tested with 512 byte page NAND device (32MByte) on Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Stefan Roese
8e1a3fe545 ppc4xx: Add AMCC Canyonlands support (460EX) (1/3)
This patch adds support for the AMCC Canyonlands 460EX evaluation
board.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Stefan Roese
e4170e5a50 ppc4xx: Fix comment in 405EX DDR2 init code
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:22:15 +01:00
Markus Brunner
772003e439 fix taihu soft spi_read
The taihu board used gpio_read_out_bit which reads the output register and not
the pin state.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
2008-03-07 09:15:26 +01:00
Stefan Roese
64cd594e62 ppc4xx: Fix acadia_nand build problem
Don't include testdram() on NAND-booting target acadia_nand. This saves
a few bytes and makes the target build clean again.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-02-25 16:50:48 +01:00
Mike Nuss
b738654d3c PPC440EPx: Optionally enable second I2C bus
The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the
PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board
code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected.

Signed-off-by: Mike Nuss <mike@terascala.com>
Cc: Stefan Roese <sr@denx.de>
2008-02-16 07:00:03 +01:00
Wolfgang Denk
865f0f9754 Coding Style Cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-23 14:31:17 +01:00
Stefan Roese
be88b16998 ppc4xx: Fix remaining CONFIG_COMMANDS in 4xx files
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-17 07:50:17 +01:00
Matthias Fuchs
83a49c8dd7 ppc4xx: Sequoia coding style cleanup and beautification
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-01-16 11:24:28 +01:00
Stefan Roese
a0dd99d51e ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit
Now that bit 29 is the USB PHY reset bit, update the Kilauea port
to remove the USB PHY reset after powerup. The CPLD will keep the
USB PHY in reset (active low) until the bit is set to 1 in
board_early_init_f().

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-14 10:05:05 +01:00
Wolfgang Denk
6eb3fb1558 Makalu: fix compile warning
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-13 16:07:44 +01:00
Wolfgang Denk
64134f0112 Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections
With recent toolchain versions, some boards would not build because
or errors like this one (here for ocotea board when building with
ELDK 4.2 beta):
ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab]

For many boards, the .bss section is big enough that it wraps around
at the end of the address space (0xFFFFFFFF), so the problem will not
be visible unless you use a 64 bit tool chain for development. On
some boards however, changes to the code size (due to different
optimizations) we bail out with section overlaps like above.

The fix is to add the NOLOAD attribute to the .bss and .sbss
sections, telling the linker that .bss does not consume any space in
the image.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-12 20:31:39 +01:00
Stefan Roese
d5a163d6ba ppc4xx: Fix sdram init on Sequoia boards
Clear possible errors in MCSR resulting from data-eye-search.
If not done, then we could get an interrupt later on when
exceptions are enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-11 15:53:58 +01:00
Niklaus Giger
4d332dbeb0 ppc4xx: Make Sequoia boot vxWorks
vxWorks expects in
TLB 0 a entry for the Machine Check interrupt
TLB 1 a entry for the RAM
TLB 2 a entry for the EBC
TLB 3 a entry for the boot flash

After changing the baudrate to 9600 I had no problems to boot the
vxWorks image as distributed by WindRiver (Revision 2.0/1 from
June 18, 2007)

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
2008-01-10 19:06:54 +01:00
Matthias Fuchs
1f84021a85 ppc4xx: assign PCI interrupts on seuqoia boards
Some operating systems rely on assigned PCI interrupts.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-01-09 06:33:03 +01:00
Stefan Roese
6399b23d60 Merge branch 'katmai-ddr-gda' 2008-01-05 10:13:40 +01:00
Stefan Roese
845c6c95db ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:12:41 +01:00
Lawrence R. Johnson
b05e8bf58b ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia board
Note: this patch changes the configuration of some GPIO registers:

   Register      Old Value   New Value
---------------  ----------  ----------
DCR GPIO0_TCR    0x0000000F  0x0000F0CF
DCR GPIO0_TSRH   0x55005000  0x00000000
DCR GPIO1_TCR    0xC2000000  0xE2000000
DCR GPIO1_TSRL   0x0C000000  0x00200000
DCR GPIO1_ISR2L  0x00050000  0x00110000

Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-04 11:39:05 +01:00
Larry Johnson
62cc3951ab PPC4xx: Remove sdram.h from board/amcc/sequoia
These definitions are now in "include/ppc440.h".

Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-04 11:37:38 +01:00
Larry Johnson
ce3902e176 PPC4xx: Use common code for Sequoia board SDRAM support
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-04 11:37:33 +01:00
Larry Johnson
c46f53333b Add definitions for 440EPx/GRx SDRAM controller to ppc440.h
This patch adds the Denali SDRAM controller definitions to "ppc440.h".
It also fixes two typos in the definitions, so the board-specific
"sdram.h" files containing these definitions are also fixed to avoid
compiler warnings.

Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:36 +01:00
Larry Johnson
d3471173e1 Use out_be32() and friends to access memory-mapped registers in sequoia.c
Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:35 +01:00
Larry Johnson
c68f59fe3e Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia
Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:35 +01:00
Stefan Roese
bf8324e4a5 ppc4xx: Add fdt support to AMCC Katmai eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:34 +01:00
Stefan Roese
136288847e ppc4xx: Bring 4xx fdt support up-to-date
This patch update the 4xx fdt support. It enabled fdt booting
on the AMCC Kilauea and Sequoia for now. More can follow later
quite easily.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:32 +01:00
Stefan Roese
7cfc12a7dc ppc4xx: 405EX: Correctly enable USB pins
This patch selects the USB data pins in the 405EX GPIO and MFC (multi
function control) registers. This is done for the AMCC Kilauea and
Makalu eval boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-08 14:47:34 +01:00
Stefan Roese
a27044b14a ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
setting the FIXD bit in the SDR0_MFR register. Here a description of the
symptoms:

Problem Description
------------------------------
If a DMA is performed between memory and PCI with the DMA 1 Controller
using prefetch, and as a result uses a special purpose buffer selected by
the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
the first part of the transfer sequence is performed twice. The
PPC440SPe PCI Controller requests more data than was needed such that in
the case of enforce memory protection, a host CPU  exception can occur.
No data is corrupted, because data transfer is stopped in the PCI
Controller. Prefetch enable is specified by setting DMA Configuration
Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.

Behavior that may be observed in a running system
---------------------------------------------------------------------------

1. DMA performance is decreased because of the double access on the PCI bus
interface.
2. If an illegal access to some address on the PCI bus is detected at the
system level, a machine check or similar system error may occur.

Workarounds Available
----------------------------------

1. Do not program prefetch. Note that a prefetch command cannot be programmed
without selecting a special purpose buffer.
2. To avoid crossing a physical boundary of the PCI slave device, add 512
bytes of address to the PCI address range.

This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
from AMCC and slighly changed.

Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-06 05:58:43 +01:00
Stefan Roese
e15e33433e ppc4xx: Kilauea: Add PCIe reset assertion upon power-up
This manual PCIe reset triggering solves the problem seen with the
Intel EPRO/1000 card, which was not detected (link not established)
upon power-up reset.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-30 07:15:41 +01:00
Stefan Roese
ecdcbd4f8c ppc4xx: Update AMCC Makalu for board rev 1.1
This patch adds changes needed for Makalu rev 1.1:

- Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
- Enable 2nd ethernet port EMAC1
- Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
- Reset PCIe ports via GPIO upon bootup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-16 14:00:59 +01:00
Stefan Roese
c9672f81f1 ppc4xx: Small AMCC Kilauea cleanup
Remove not needed pci_target_init() function.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-15 14:25:09 +01:00
Stefan Roese
654f38b3a3 ppc4xx: Make output a little shorter on PCIe detection
Now not max 3 lines but 2 lines are printed per PCIe port.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-05 07:43:05 +01:00
Stefan Roese
3d6cb3b24a ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support
This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-03 12:08:28 +01:00
Stefan Roese
ea2e142843 ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
353f2688b4 ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Eugene O'Brien
9f798766aa ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
882ae41274 ppc4xx: Rework of 4xx serial driver (2)
Change all linker scripts to reference the changed driver name 4xx_uart.o.

Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
211ea91ac6 ppc4xx: Add initial AMCC Makalu 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
770c7af580 ppc4xx: Fix size setup in Kilauea DDR2 init routine
The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.

This patch also does a little cleanup and adds a comment here.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
d4cb2d1794 ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
fd671802b6 ppc4xx: Enable device tree support (fdt) on Kilauea per default
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.

This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
566806ca1a ppc4xx: Add initial AMCC Kilauea 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00