Commit graph

44828 commits

Author SHA1 Message Date
Simon Glass
000f15fa15 dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
be7890927a dm: tegra: Convert USB setup to livetree
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
66de3eee79 tegra: tegra124: Add a PMC syscon driver
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed. Enable it for tegra124
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
9b6b3c1b50 tegra: spl: Enable debug UART
Enable the debug UART in SPL to allow early serial output even if the
standard UART does not work (e.g. due to driver model problem).

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
0f6507a7e4 dm: core: Fix up ofnode_get_addr_index() for 64-bit values
At present this function only supports 32-bit (single-cell) values. Update
it to support two-cell values also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
dcf988525f dm: core: Add ofnode_read_resource()
We sometimes need to read a resource from an arbitrary node. In any case
for consistency we should not put the live-tree switching code in
a dev_read_...() function. Update this to suit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
c61d0009fe console: simplify puts()
Current puts() and putc() have similar #ifdef / if() conditionals.
Make puts() iterate over putc() to avoid code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
47b98ad0f6 sandbox: remove os_putc() and os_puts()
They are unused since commit d8c6fb8ced ("sandbox: Drop special
case console code for sandbox").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Masahiro Yamada
fd73621cba dm: ofnode: change return type of dev_read_prop() to opaque pointer
DT property values can be strings as well as integers.  This is why
of_get_property/fdt_getprop returns an opaque pointer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Philipp Tomsich
00b26f7cdb dm: Fix typo in include-guard for dm-structs.h
The include-guard for dm-structs.h was misspelled as __DT_STTUCTS.
Change it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
db13a768a0 cmd: scsi: Fix null pointer dereference in 'scsi reset'
During 'scsi reset', scsi_bus_reset() is called with udevice pointed
to NULL, which causes exception. As a temporary fix, disable the call
for DM SCSI for now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Bin Meng
9c1390d4b9 dm: ahci: Avoid scsi_scan_dev() in ahci_probe_scsi()
Running 'scsi scan' command causes scsi_scan_dev() to be called,
from which device_probe() is called and consequently AHCI driver
probe routine will be called as SCSI driver's parent, and finally
ahci_probe_scsi() calls scsi_scan_dev() again.

Remove the call to scsi_scan_dev() in ahci_probe_scsi().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 12:02:47 -06:00
Kever Yang
2672233525 rockchip: puma-rk3399: remove duplicate code (merge artifact)
A few lines (defines and declarations) had been duplicated when the
puma-rk3399 board was initially merged.  This removes the duplicates
and changes the style to use local constants instead of pasted
literals.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[fixed up commit-message & converted to use 'const u32':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
86b1122a84 rockchip: add u-boot specific dts for rk3036 sdk
Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
77c17f4354 rockchip: use puts instead of printf when back to bootrom
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
d26bfa73ed rockchip: enable SPL_LIBGENERIC for rk3036 based boards
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
8b154ed61c rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
7f38025824 rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board
RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
1fc50d727f sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation
SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.

Signed-off-by: Andy Yan <andyshrk@gmail.com>

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/sandbox/cpu/start.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:04 +02:00
Andy Yan
9eea50162c microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
2b71d098ee powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f5868a5da1 mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Andy Yan
f1896c45cb spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
a1903c18db rockchip: firefly: Add "usb start" to auto-start USB device
Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't
need to input "usb start" in command line of u-boot console,it
can auto-start the USB device,after that usb keyboard can work.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
af83064769 rockchip: firefly: Set the environment variable 'usbkbd' to the stdin
Add the 'usbkbd' environment variable to the 'stdin', the contents of
the keyboard input can be auto-displayed on the serial terminal,so
you don't need to manually set the environment variable 'stdin'.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Leo Wen
73f255b7dc rockchip: firefly: Add some macros to enable the usb keyboard
Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the
firefly-rk3288_defconfig,can support usb keyboard device when these four
macros are enabled.

Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:03 +02:00
Philipp Tomsich
c0508e427f rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via Kconfig
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h.  This change implies these options
through Kconfig.

These need to always be active for the RK3399, as follows:
 - SPL_SERIAL_SUPPORT is needed to pass the SPL build
 - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Romain Perier
478e6f2e94 rockchip: rk3288: Add support for drive-strength in PINCTRL
Currently, drive-strenght to 12ma are described and supposed to be used
on RK3288. However, the pinctrl driver for this SoC only handles muxing
and pull up/pull down via PU/PD control registers. So complex IPs like
GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.

This commit adds support for handling drive-strength of 12ma, when it's
defined in the DT.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Kever Yang
42ec247e69 rockchip: use UUID for root partitions
We use to use /dev/mmcbl0p7 as root partition, and pass it
to kernel by cmdline, but the mmc number in kernel in not
fixed, we need to change the bootargs to adapt it from time
to time.
We can use the UUID to fix it, the ID is from:
https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/
ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3
ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
4436c5db05 rockchip: dts: rk3399-puma: put EFI partition entries at 2MB
When creating a EFI/GUID partition map for the RK3399-Q7 through
U-Boot, the partition entries should be places at a 1MB offset from
the start of the device to give us space for the environment (at 16KB
on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the
image payload (at 256KB on SD/MMC devices).

This change sets this up through the u-boot,efi-partition-entries-offset
/config property in the RK3399-Q7 DTSI.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
56f580d3eb rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL
As our SPL stage can grow quite large (80KB+ are not unusual) on the
RK3399-Q7, the default setting for the environment location (in
include/configs/rockchip-common.h) can overlap our SPL.

This change finally makes use of the 'u-boot,mmc-env-offset' DTS
property to override the environment location and put it at 16KB into
the device, which is right before the SPL (located at 32KB).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
01106571ad rockchip: clk: rk3399: remove unused fields from priv-structures
This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
80c83e8190 rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
cdc6080a28 rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc
The clk driver for the RK3368 picked the wrong data structure's size
for its auto-alloc size: the size was calculated on the structure
representing the CRU hardware block instead of the priv structure.
As the CRU's register file is much larger than the driver's priv,
this did not cause any pain (except wasting memory).

Fix this by using the correct data structure's size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Philipp Tomsich
700f3108d3 rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word).  Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction).  To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.

To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.

This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27 14:59:02 +02:00
Kever Yang
06f4e36baf rockchip: pwm: add mask for config setting
Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.

Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
3030c951f1 power: pwm_regulator: remove redundant code
The regulator_enable() should be called from upper layer like
regulators_enable_boot_on(), remove it from pwm regulator driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up typo in commit message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
f339bca248 power: pwm_regulator: fix the pwm_set_config parameter order
The rkpwm reg order has fixed by below patch:
e3ef41d rockchip: pwm: fix the register layout for the PWM controller

We need to correct the parameter order for pwm_set_config() to make
the pwm regulator works correctly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
7ba3182e2d rockchip: dts: correct vdd_log setting for firefly-rk3399
Add regulator-init-microvolt for driver to init the regulator,
and the min output value is not 800000mV for the PWM2 io domain has
changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to
correct it with the value measured when PWM2 output HIGH.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Kever Yang
56f2dd0aed rockchip: dts: firefly using ddr3 1600
According to my test, some of firefly-rk3399 hang after dram init
when using ddr3-1333 config, while using ddr3-1600 config works
for all the board I have test.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Wadim Egorov
c03635c3d1 rockchip: phycore: Add ID page of M24C32-D EEPROM
The Identification Page (32 byte) is an additional page which can be written
and (later) permanently locked in Read-only mode.

phyCORE-RK3288 SoMs are using this page to describe the module variant.
This page also contains a MAC.

Our boards can be equipped with a different amount of EEPROMs. To make
this more transparent let's add an alias for the eeprom which stores the
module variant.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
3641d346ea rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Romain Perier
a98fc4325e rockchip: rk3288: Remove phy reset GPIO pull up
We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.

This commit removes pull up for GPIO4B0.

Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:01 +02:00
Philipp Tomsich
928979cb2b rockchip: efuse: dm: change to use dev_read_addr
This changes the rockchip-efuse driver to use dev_read_addr instead of
devfdt_get_addr.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Philipp Tomsich
cb91173a7f rockchip: timer: make register sizes explicit
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.

Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Meng Dongyang
0124062853 rockchip: dts: rk3229: add dwc2 node for fastboot
Add dwc2 node for fastboot to init dwc2 controller.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27 14:59:00 +02:00
Tom Rini
f19955a014 Merge git://git.denx.de/u-boot-uniphier 2017-07-26 11:29:25 -04:00
Tom Rini
0ddc9c1722 Merge git://git.denx.de/u-boot-mips 2017-07-26 11:29:20 -04:00
Bin Meng
dc5210a20d MAINTAINERS: Update maintainer for x86
This adds myself as one of the x86 maintainers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-26 11:29:16 -04:00
Tom Rini
25fa0b930f FIT: List kernel_noload in the list of types
In the source_file_format.txt file we talk about how to construct a
valid FIT image.  While it already says to look at the source for the
full list, add kernel_noload to the explicit list of types.  This is
arguably the most important type to use as most often we are including a
kernel that will run from wherever it is loaded into memory and execute.

This for example, allows you to create a single FIT image for Linux that
can be used on both OMAP and i.MX devices as the kernel will not need to
be moved in memory.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:29:15 -04:00