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ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
Factor out center_dq_windows(), which is common code between stage 2 and stage 3 of the calibration again and cater for the minor differences. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
parent
afb3eb84b8
commit
ffb8b66ea8
1 changed files with 88 additions and 89 deletions
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@ -2115,13 +2115,90 @@ static int get_window_mid_index(const int write, int *left_edge,
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return min_index;
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}
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/**
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* center_dq_windows() - Center the DQ/DQS windows
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* @write: Perform read (Stage 2) or write (Stage 3) calibration
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* @left_edge: Left edge of the DQ/DQS phase
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* @right_edge: Right edge of the DQ/DQS phase
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* @mid_min: Adjusted DQ/DQS phase middle setting
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* @orig_mid_min: Original DQ/DQS phase middle setting
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* @min_index: DQ/DQS phase middle setting index
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* @test_bgn: Rank number to begin the test
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* @dq_margin: Amount of shift for the DQ
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* @dqs_margin: Amount of shift for the DQS
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*
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* Align the DQ/DQS windows in each group.
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*/
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static void center_dq_windows(const int write, int *left_edge, int *right_edge,
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const int mid_min, const int orig_mid_min,
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const int min_index, const int test_bgn,
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int *dq_margin, int *dqs_margin)
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{
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const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
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const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
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RW_MGR_MEM_DQ_PER_READ_DQS;
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const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
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SCC_MGR_IO_IN_DELAY_OFFSET;
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const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
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u32 temp_dq_io_delay1, temp_dq_io_delay2;
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int shift_dq, i, p;
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/* Initialize data for export structures */
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*dqs_margin = delay_max + 1;
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*dq_margin = delay_max + 1;
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/* add delay to bring centre of all DQ windows to the same "level" */
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for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
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/* Use values before divide by 2 to reduce round off error */
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shift_dq = (left_edge[i] - right_edge[i] -
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(left_edge[min_index] - right_edge[min_index]))/2 +
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(orig_mid_min - mid_min);
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debug_cond(DLEVEL == 2,
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"vfifo_center: before: shift_dq[%u]=%d\n",
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i, shift_dq);
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temp_dq_io_delay1 = readl(addr + (p << 2));
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temp_dq_io_delay2 = readl(addr + (i << 2));
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if (shift_dq + temp_dq_io_delay1 > delay_max)
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shift_dq = delay_max - temp_dq_io_delay2;
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else if (shift_dq + temp_dq_io_delay1 < 0)
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shift_dq = -temp_dq_io_delay1;
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debug_cond(DLEVEL == 2,
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"vfifo_center: after: shift_dq[%u]=%d\n",
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i, shift_dq);
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if (write)
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scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
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else
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scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
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scc_mgr_load_dq(p);
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debug_cond(DLEVEL == 2,
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"vfifo_center: margin[%u]=[%d,%d]\n", i,
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left_edge[i] - shift_dq + (-mid_min),
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right_edge[i] + shift_dq - (-mid_min));
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/* To determine values for export structures */
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if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
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*dq_margin = left_edge[i] - shift_dq + (-mid_min);
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if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
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*dqs_margin = right_edge[i] + shift_dq - (-mid_min);
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}
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}
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/* per-bit deskew DQ and center */
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static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
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uint32_t use_read_test, uint32_t update_fom)
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{
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uint32_t p, min_index;
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int i;
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int i, min_index;
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/*
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* Store these as signed since there are comparisons with
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* signed numbers.
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@ -2130,13 +2207,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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uint32_t sticky_bit_chk;
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int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
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int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
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int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
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int32_t mid;
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int32_t orig_mid_min, mid_min;
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int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
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final_dqs_en;
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int32_t new_dqs, start_dqs, start_dqs_en, final_dqs, final_dqs_en;
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int32_t dq_margin, dqs_margin;
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uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
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uint32_t addr;
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int ret;
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@ -2225,49 +2298,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
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IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
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new_dqs, mid_min);
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/* Initialize data for export structures */
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dqs_margin = IO_IO_IN_DELAY_MAX + 1;
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dq_margin = IO_IO_IN_DELAY_MAX + 1;
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/* add delay to bring centre of all DQ windows to the same "level" */
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for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
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/* Use values before divide by 2 to reduce round off error */
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shift_dq = (left_edge[i] - right_edge[i] -
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(left_edge[min_index] - right_edge[min_index]))/2 +
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(orig_mid_min - mid_min);
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debug_cond(DLEVEL == 2,
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"vfifo_center: before: shift_dq[%u]=%d\n",
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i, shift_dq);
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addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
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temp_dq_in_delay1 = readl(addr + (p << 2));
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temp_dq_in_delay2 = readl(addr + (i << 2));
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if (shift_dq + temp_dq_in_delay1 > IO_IO_IN_DELAY_MAX)
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shift_dq = IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
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else if (shift_dq + temp_dq_in_delay1 < 0)
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shift_dq = -temp_dq_in_delay1;
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debug_cond(DLEVEL == 2,
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"vfifo_center: after: shift_dq[%u]=%d\n",
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i, shift_dq);
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final_dq[i] = temp_dq_in_delay1 + shift_dq;
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scc_mgr_set_dq_in_delay(p, final_dq[i]);
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scc_mgr_load_dq(p);
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debug_cond(DLEVEL == 2,
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"vfifo_center: margin[%u]=[%d,%d]\n", i,
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left_edge[i] - shift_dq + (-mid_min),
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right_edge[i] + shift_dq - (-mid_min));
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/* To determine values for export structures */
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if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
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dq_margin = left_edge[i] - shift_dq + (-mid_min);
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if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
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dqs_margin = right_edge[i] + shift_dq - (-mid_min);
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}
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/* Add delay to bring centre of all DQ windows to the same "level". */
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center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
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min_index, test_bgn, &dq_margin, &dqs_margin);
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final_dqs = new_dqs;
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if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
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@ -2852,7 +2885,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
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static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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uint32_t write_group, uint32_t test_bgn)
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{
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uint32_t i, p, min_index;
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uint32_t i, min_index;
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int32_t d;
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/*
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* Store these as signed since there are comparisons with
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@ -2864,9 +2897,8 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
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int32_t mid;
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int32_t mid_min, orig_mid_min;
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int32_t new_dqs, start_dqs, shift_dq;
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int32_t new_dqs, start_dqs;
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int32_t dq_margin, dqs_margin, dm_margin;
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uint32_t temp_dq_out1_delay;
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uint32_t addr;
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int ret;
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@ -2915,43 +2947,10 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
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mid_min = 0;
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debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
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mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
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/* Initialize data for export structures */
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dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
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dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
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/* add delay to bring centre of all DQ windows to the same "level" */
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for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
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/* Use values before divide by 2 to reduce round off error */
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shift_dq = (left_edge[i] - right_edge[i] -
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(left_edge[min_index] - right_edge[min_index]))/2 +
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(orig_mid_min - mid_min);
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debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
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[%u]=%d\n", __func__, __LINE__, i, shift_dq);
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addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
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temp_dq_out1_delay = readl(addr + (i << 2));
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if (shift_dq + (int32_t)temp_dq_out1_delay >
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(int32_t)IO_IO_OUT1_DELAY_MAX) {
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shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
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} else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
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shift_dq = -(int32_t)temp_dq_out1_delay;
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}
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debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
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i, shift_dq);
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scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
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scc_mgr_load_dq(i);
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debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
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left_edge[i] - shift_dq + (-mid_min),
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right_edge[i] + shift_dq - (-mid_min));
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/* To determine values for export structures */
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if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
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dq_margin = left_edge[i] - shift_dq + (-mid_min);
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if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
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dqs_margin = right_edge[i] + shift_dq - (-mid_min);
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}
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/* Add delay to bring centre of all DQ windows to the same "level". */
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center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
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min_index, 0, &dq_margin, &dqs_margin);
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/* Move DQS */
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scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
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