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mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: Stefan Roese <sr@denx.de>
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2 changed files with 65 additions and 0 deletions
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@ -775,6 +775,7 @@ M: Aaron Williams <awilliams@marvell.com>
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S: Maintained
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F: arch/mips/mach-octeon/
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F: arch/mips/include/asm/arch-octeon/
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F: arch/mips/dts/mrvl,cn73xx.dtsi
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MMC
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M: Peng Fan <peng.fan@nxp.com>
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64
arch/mips/dts/mrvl,cn73xx.dtsi
Normal file
64
arch/mips/dts/mrvl,cn73xx.dtsi
Normal file
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@ -0,0 +1,64 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell / Cavium Inc. CN73xx
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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soc0: soc@0 {
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interrupt-parent = <&ciu3>;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges; /* Direct mapping */
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ciu3: interrupt-controller@1010000000000 {
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compatible = "cavium,octeon-7890-ciu3";
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interrupt-controller;
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/*
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* Interrupts are specified by two parts:
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* 1) Source number (20 significant bits)
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* 2) Trigger type: (4 == level, 1 == edge)
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*/
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x10100 0x00000000 0x0 0xb0000000>;
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};
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bootbus: bootbus@1180000000000 {
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compatible = "cavium,octeon-3860-bootbus","simple-bus";
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reg = <0x11800 0x00000000 0x0 0x200>;
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/* The chip select number and offset */
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#address-cells = <2>;
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/* The size of the chip select region */
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#size-cells = <1>;
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};
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reset: reset@1180006001600 {
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compatible = "mrvl,cn7xxx-rst";
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reg = <0x11800 0x06001600 0x0 0x200>;
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};
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uart0: serial@1180000000800 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000800 0x0 0x400>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <0x08000 4>;
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};
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uart1: serial@1180000000c00 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000c00 0x0 0x400>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <0x08040 4>;
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};
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};
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};
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