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armv8: ls1046aqds: add lpuart support

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LPUART0 is used by default, and it's using platform clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shaohui Xie 2016-10-28 14:24:02 +08:00 committed by York Sun
parent 9b46213b4f
commit fdc2b54cb8
7 changed files with 131 additions and 0 deletions
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1
arch/arm/dts/Makefile
View file

@ -151,6 +151,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1046a-qds-duart.dtb \
fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \

16
arch/arm/dts/fsl-ls1046a-qds-lpuart.dts Normal file
View file

@ -0,0 +1,16 @@
/*
* Device Tree file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "fsl-ls1046a-qds.dtsi"
/ {
chosen {
stdout-path = &lpuart0;
};
};

4
arch/arm/dts/fsl-ls1046a-qds.dtsi
View file

@ -75,3 +75,7 @@
&duart1 {
status = "okay";
};
&lpuart0 {
status = "okay";
};

54
arch/arm/dts/fsl-ls1046a.dtsi
View file

@ -151,6 +151,60 @@
clocks = <&clockgen 4 0>;
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <0 48 0x4>;
clocks = <&clockgen 4 0>;
clock-names = "ipg";
status = "disabled";
};
lpuart1: serial@2960000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
interrupts = <0 49 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart2: serial@2970000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
interrupts = <0 50 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart3: serial@2980000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
interrupts = <0 51 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart4: serial@2990000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
interrupts = <0 52 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart5: serial@29a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
interrupts = <0 53 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
#address-cells = <1>;

18
board/freescale/ls1046aqds/ls1046aqds.c
View file

@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
#ifdef CONFIG_LPUART
u32 get_lpuart_clk(void)
{
return gd->bus_clk;
}
#endif
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
@ -157,6 +164,9 @@ int board_early_init_f(void)
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
@ -175,6 +185,14 @@ int board_early_init_f(void)
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif
#ifdef CONFIG_LPUART
/* We use lpuart0 as system console */
uart = QIXIS_READ(brdcfg[14]);
uart &= ~CFG_UART_MUX_MASK;
uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
QIXIS_WRITE(brdcfg[14], uart);
#endif
return 0;
}

30
configs/ls1046aqds_lpuart_defconfig Normal file
View file

@ -0,0 +1,30 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_FSL_DSPI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y

8
include/configs/ls1046aqds.h
View file

@ -127,6 +127,14 @@ unsigned long get_board_ddr_clk(void);
#endif
#endif
/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#define CFG_UART_MUX_MASK 0x6
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x2
#endif
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI