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dm: tegra: spi: Convert to driver model
This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
d2f60f9332
commit
fda6fac39b
12 changed files with 415 additions and 679 deletions
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@ -1,41 +0,0 @@
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/*
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* NVIDIA Tegra SPI controller
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*
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* Copyright 2010-2013 NVIDIA Corporation
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA114_SPI_H_
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#define _TEGRA114_SPI_H_
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#include <asm/types.h>
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int tegra114_spi_init(int *node_list, int count);
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int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
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struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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void tegra114_spi_free_slave(struct spi_slave *slave);
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int tegra114_spi_claim_bus(struct spi_slave *slave);
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void tegra114_spi_cs_activate(struct spi_slave *slave);
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void tegra114_spi_cs_deactivate(struct spi_slave *slave);
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int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags);
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#endif /* _TEGRA114_SPI_H_ */
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@ -1,41 +0,0 @@
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/*
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* NVIDIA Tegra20 SPI-FLASH controller
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*
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* Copyright 2010-2012 NVIDIA Corporation
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA20_SPI_H_
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#define _TEGRA20_SPI_H_
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#include <asm/types.h>
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int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
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struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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void tegra20_spi_free_slave(struct spi_slave *slave);
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int tegra20_spi_init(int *node_list, int count);
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int tegra20_spi_claim_bus(struct spi_slave *slave);
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void tegra20_spi_cs_activate(struct spi_slave *slave);
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void tegra20_spi_cs_deactivate(struct spi_slave *slave);
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int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags);
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#endif /* _TEGRA20_SPI_H_ */
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@ -1,41 +0,0 @@
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/*
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* NVIDIA Tegra SPI-SLINK controller
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*
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* Copyright 2010-2013 NVIDIA Corporation
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TEGRA30_SPI_H_
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#define _TEGRA30_SPI_H_
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#include <asm/types.h>
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int tegra30_spi_init(int *node_list, int count);
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int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
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struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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void tegra30_spi_free_slave(struct spi_slave *slave);
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int tegra30_spi_claim_bus(struct spi_slave *slave);
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void tegra30_spi_cs_activate(struct spi_slave *slave);
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void tegra30_spi_cs_deactivate(struct spi_slave *slave);
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int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags);
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#endif /* _TEGRA30_SPI_H_ */
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@ -114,9 +114,8 @@ int board_init(void)
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clock_init();
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clock_init();
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clock_verify();
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clock_verify();
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#ifdef CONFIG_FDT_SPI
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#ifdef CONFIG_TEGRA_SPI
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pin_mux_spi();
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pin_mux_spi();
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spi_init();
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#endif
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#endif
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#ifdef CONFIG_PWM_TEGRA
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#ifdef CONFIG_PWM_TEGRA
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@ -40,7 +40,6 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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obj-$(CONFIG_FDT_SPI) += fdt_spi.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
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obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
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obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
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obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
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/*
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* Common fdt based SPI driver front end
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*
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* Copyright (c) 2013 NVIDIA Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra20/tegra20_sflash.h>
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#include <asm/arch-tegra20/tegra20_slink.h>
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#include <asm/arch-tegra114/tegra114_spi.h>
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#include <spi.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct fdt_spi_driver {
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int compat;
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int max_ctrls;
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int (*init)(int *node_list, int count);
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int (*claim_bus)(struct spi_slave *slave);
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int (*release_bus)(struct spi_slave *slave);
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int (*cs_is_valid)(unsigned int bus, unsigned int cs);
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struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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void (*free_slave)(struct spi_slave *slave);
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void (*cs_activate)(struct spi_slave *slave);
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void (*cs_deactivate)(struct spi_slave *slave);
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int (*xfer)(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags);
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};
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static struct fdt_spi_driver fdt_spi_drivers[] = {
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#ifdef CONFIG_TEGRA20_SFLASH
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{
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.compat = COMPAT_NVIDIA_TEGRA20_SFLASH,
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.max_ctrls = 1,
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.init = tegra20_spi_init,
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.claim_bus = tegra20_spi_claim_bus,
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.cs_is_valid = tegra20_spi_cs_is_valid,
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.setup_slave = tegra20_spi_setup_slave,
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.free_slave = tegra20_spi_free_slave,
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.cs_activate = tegra20_spi_cs_activate,
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.cs_deactivate = tegra20_spi_cs_deactivate,
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.xfer = tegra20_spi_xfer,
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},
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#endif
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#ifdef CONFIG_TEGRA20_SLINK
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{
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.compat = COMPAT_NVIDIA_TEGRA20_SLINK,
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.max_ctrls = CONFIG_TEGRA_SLINK_CTRLS,
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.init = tegra30_spi_init,
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.claim_bus = tegra30_spi_claim_bus,
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.cs_is_valid = tegra30_spi_cs_is_valid,
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.setup_slave = tegra30_spi_setup_slave,
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.free_slave = tegra30_spi_free_slave,
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.cs_activate = tegra30_spi_cs_activate,
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.cs_deactivate = tegra30_spi_cs_deactivate,
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.xfer = tegra30_spi_xfer,
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},
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#endif
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#ifdef CONFIG_TEGRA114_SPI
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{
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.compat = COMPAT_NVIDIA_TEGRA114_SPI,
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.max_ctrls = CONFIG_TEGRA114_SPI_CTRLS,
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.init = tegra114_spi_init,
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.claim_bus = tegra114_spi_claim_bus,
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.cs_is_valid = tegra114_spi_cs_is_valid,
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.setup_slave = tegra114_spi_setup_slave,
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.free_slave = tegra114_spi_free_slave,
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.cs_activate = tegra114_spi_cs_activate,
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.cs_deactivate = tegra114_spi_cs_deactivate,
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.xfer = tegra114_spi_xfer,
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},
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#endif
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};
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static struct fdt_spi_driver *driver;
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (!driver)
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return 0;
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else if (!driver->cs_is_valid)
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return 1;
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else
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return driver->cs_is_valid(bus, cs);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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if (!driver || !driver->setup_slave)
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return NULL;
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return driver->setup_slave(bus, cs, max_hz, mode);
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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if (driver && driver->free_slave)
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return driver->free_slave(slave);
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}
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static int spi_init_driver(struct fdt_spi_driver *driver)
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{
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int count;
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int node_list[driver->max_ctrls];
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
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driver->compat,
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node_list,
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driver->max_ctrls);
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return driver->init(node_list, count);
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}
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void spi_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) {
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driver = &fdt_spi_drivers[i];
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if (!spi_init_driver(driver))
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break;
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}
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if (i == ARRAY_SIZE(fdt_spi_drivers))
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driver = NULL;
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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if (!driver)
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return 1;
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if (!driver->claim_bus)
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return 0;
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return driver->claim_bus(slave);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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if (driver && driver->release_bus)
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driver->release_bus(slave);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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if (driver && driver->cs_activate)
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driver->cs_activate(slave);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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if (driver && driver->cs_deactivate)
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driver->cs_deactivate(slave);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *data_out, void *data_in, unsigned long flags)
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{
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if (!driver || !driver->xfer)
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return -1;
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return driver->xfer(slave, bitlen, data_out, data_in, flags);
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}
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <malloc.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra114/tegra114_spi.h>
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#include <spi.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include "tegra_spi.h"
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -104,130 +103,63 @@ struct spi_regs {
|
||||||
u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
|
u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_ctrl {
|
struct tegra114_spi_priv {
|
||||||
struct spi_regs *regs;
|
struct spi_regs *regs;
|
||||||
unsigned int freq;
|
unsigned int freq;
|
||||||
unsigned int mode;
|
unsigned int mode;
|
||||||
int periph_id;
|
int periph_id;
|
||||||
int valid;
|
int valid;
|
||||||
|
int last_transaction_us;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_slave {
|
static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
|
||||||
struct spi_slave slave;
|
|
||||||
struct tegra_spi_ctrl *ctrl;
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
|
|
||||||
|
|
||||||
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
|
|
||||||
{
|
{
|
||||||
return container_of(slave, struct tegra_spi_slave, slave);
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
const void *blob = gd->fdt_blob;
|
||||||
|
int node = bus->of_offset;
|
||||||
|
|
||||||
|
plat->base = fdtdec_get_addr(blob, node, "reg");
|
||||||
|
plat->periph_id = clock_decode_periph_id(blob, node);
|
||||||
|
|
||||||
|
if (plat->periph_id == PERIPH_ID_NONE) {
|
||||||
|
debug("%s: could not decode periph id %d\n", __func__,
|
||||||
|
plat->periph_id);
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
/* Use 500KHz as a suitable default */
|
||||||
{
|
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||||
if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
|
500000);
|
||||||
|
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
||||||
|
"spi-deactivate-delay", 0);
|
||||||
|
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
||||||
|
__func__, plat->base, plat->periph_id, plat->frequency,
|
||||||
|
plat->deactivate_delay_us);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
else
|
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
|
static int tegra114_spi_probe(struct udevice *bus)
|
||||||
unsigned int max_hz, unsigned int mode)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi;
|
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
|
priv->regs = (struct spi_regs *)plat->base;
|
||||||
bus, cs, max_hz, mode);
|
|
||||||
|
|
||||||
if (!spi_cs_is_valid(bus, cs)) {
|
priv->last_transaction_us = timer_get_us();
|
||||||
printf("SPI error: unsupported bus %d / chip select %d\n",
|
priv->freq = plat->frequency;
|
||||||
bus, cs);
|
priv->periph_id = plat->periph_id;
|
||||||
return NULL;
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (max_hz > TEGRA_SPI_MAX_FREQ) {
|
static int tegra114_spi_claim_bus(struct udevice *bus)
|
||||||
printf("SPI error: unsupported frequency %d Hz. Max frequency"
|
|
||||||
" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
|
|
||||||
if (!spi) {
|
|
||||||
printf("SPI error: malloc of SPI structure failed\n");
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
spi->ctrl = &spi_ctrls[bus];
|
|
||||||
if (!spi->ctrl) {
|
|
||||||
printf("SPI error: could not find controller for bus %d\n",
|
|
||||||
bus);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (max_hz < spi->ctrl->freq) {
|
|
||||||
debug("%s: limiting frequency from %u to %u\n", __func__,
|
|
||||||
spi->ctrl->freq, max_hz);
|
|
||||||
spi->ctrl->freq = max_hz;
|
|
||||||
}
|
|
||||||
spi->ctrl->mode = mode;
|
|
||||||
|
|
||||||
return &spi->slave;
|
|
||||||
}
|
|
||||||
|
|
||||||
void tegra114_spi_free_slave(struct spi_slave *slave)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
struct spi_regs *regs = priv->regs;
|
||||||
free(spi);
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra114_spi_init(int *node_list, int count)
|
|
||||||
{
|
|
||||||
struct tegra_spi_ctrl *ctrl;
|
|
||||||
int i;
|
|
||||||
int node = 0;
|
|
||||||
int found = 0;
|
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
|
||||||
ctrl = &spi_ctrls[i];
|
|
||||||
node = node_list[i];
|
|
||||||
|
|
||||||
ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
|
|
||||||
node, "reg");
|
|
||||||
if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
|
|
||||||
debug("%s: no spi register found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
|
|
||||||
"spi-max-frequency", 0);
|
|
||||||
if (!ctrl->freq) {
|
|
||||||
debug("%s: no spi max frequency found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
|
|
||||||
if (ctrl->periph_id == PERIPH_ID_NONE) {
|
|
||||||
debug("%s: could not decode periph id\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->valid = 1;
|
|
||||||
found = 1;
|
|
||||||
|
|
||||||
debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
|
|
||||||
__func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
|
|
||||||
}
|
|
||||||
|
|
||||||
return !found;
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra114_spi_claim_bus(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
|
||||||
|
|
||||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||||
clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
|
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
||||||
spi->ctrl->freq);
|
|
||||||
|
|
||||||
/* Clear stale status here */
|
/* Clear stale status here */
|
||||||
setbits_le32(®s->fifo_status,
|
setbits_le32(®s->fifo_status,
|
||||||
|
@ -244,33 +176,64 @@ int tegra114_spi_claim_bus(struct spi_slave *slave)
|
||||||
|
|
||||||
/* Set master mode and sw controlled CS */
|
/* Set master mode and sw controlled CS */
|
||||||
setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
|
setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
|
||||||
(spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
|
(priv->mode << SPI_CMD1_MODE_SHIFT));
|
||||||
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
|
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra114_spi_cs_activate(struct spi_slave *slave)
|
/**
|
||||||
|
* Activate the CS by driving it LOW
|
||||||
|
*
|
||||||
|
* @param slave Pointer to spi_slave to which controller has to
|
||||||
|
* communicate with
|
||||||
|
*/
|
||||||
|
static void spi_cs_activate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL);
|
/* If it's too soon to do another transaction, wait */
|
||||||
|
if (pdata->deactivate_delay_us &&
|
||||||
|
priv->last_transaction_us) {
|
||||||
|
ulong delay_us; /* The delay completed so far */
|
||||||
|
delay_us = timer_get_us() - priv->last_transaction_us;
|
||||||
|
if (delay_us < pdata->deactivate_delay_us)
|
||||||
|
udelay(pdata->deactivate_delay_us - delay_us);
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra114_spi_cs_deactivate(struct spi_slave *slave)
|
clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
|
||||||
{
|
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
|
||||||
|
|
||||||
setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
/**
|
||||||
const void *data_out, void *data_in, unsigned long flags)
|
* Deactivate the CS by driving it HIGH
|
||||||
|
*
|
||||||
|
* @param slave Pointer to spi_slave to which controller has to
|
||||||
|
* communicate with
|
||||||
|
*/
|
||||||
|
static void spi_cs_deactivate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
|
||||||
|
|
||||||
|
/* Remember time of this transaction so we can honour the bus delay */
|
||||||
|
if (pdata->deactivate_delay_us)
|
||||||
|
priv->last_transaction_us = timer_get_us();
|
||||||
|
|
||||||
|
debug("Deactivate CS, bus '%s'\n", bus->name);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||||
|
const void *data_out, void *data_in,
|
||||||
|
unsigned long flags)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev->parent;
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
struct spi_regs *regs = priv->regs;
|
||||||
u32 reg, tmpdout, tmpdin = 0;
|
u32 reg, tmpdout, tmpdin = 0;
|
||||||
const u8 *dout = data_out;
|
const u8 *dout = data_out;
|
||||||
u8 *din = data_in;
|
u8 *din = data_in;
|
||||||
|
@ -278,7 +241,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
|
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
|
||||||
__func__, slave->bus, slave->cs, dout, din, bitlen);
|
__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
|
||||||
if (bitlen % 8)
|
if (bitlen % 8)
|
||||||
return -1;
|
return -1;
|
||||||
num_bytes = bitlen / 8;
|
num_bytes = bitlen / 8;
|
||||||
|
@ -291,13 +254,13 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
|
|
||||||
clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL,
|
clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL,
|
||||||
SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
|
SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
|
||||||
(slave->cs << SPI_CMD1_CS_SEL_SHIFT));
|
(spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
|
||||||
|
|
||||||
/* set xfer size to 1 block (32 bits) */
|
/* set xfer size to 1 block (32 bits) */
|
||||||
writel(0, ®s->dma_blk);
|
writel(0, ®s->dma_blk);
|
||||||
|
|
||||||
if (flags & SPI_XFER_BEGIN)
|
if (flags & SPI_XFER_BEGIN)
|
||||||
spi_cs_activate(slave);
|
spi_cs_activate(dev);
|
||||||
|
|
||||||
/* handle data in 32-bit chunks */
|
/* handle data in 32-bit chunks */
|
||||||
while (num_bytes > 0) {
|
while (num_bytes > 0) {
|
||||||
|
@ -383,7 +346,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flags & SPI_XFER_END)
|
if (flags & SPI_XFER_END)
|
||||||
spi_cs_deactivate(slave);
|
spi_cs_deactivate(dev);
|
||||||
|
|
||||||
debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
|
debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
|
||||||
__func__, tmpdin, readl(®s->fifo_status));
|
__func__, tmpdin, readl(®s->fifo_status));
|
||||||
|
@ -394,5 +357,56 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
|
||||||
|
{
|
||||||
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
if (speed > plat->frequency)
|
||||||
|
speed = plat->frequency;
|
||||||
|
priv->freq = speed;
|
||||||
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
|
||||||
|
{
|
||||||
|
struct tegra114_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
priv->mode = mode;
|
||||||
|
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_spi_ops tegra114_spi_ops = {
|
||||||
|
.claim_bus = tegra114_spi_claim_bus,
|
||||||
|
.xfer = tegra114_spi_xfer,
|
||||||
|
.set_speed = tegra114_spi_set_speed,
|
||||||
|
.set_mode = tegra114_spi_set_mode,
|
||||||
|
/*
|
||||||
|
* cs_info is not needed, since we require all chip selects to be
|
||||||
|
* in the device tree explicitly
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id tegra114_spi_ids[] = {
|
||||||
|
{ .compatible = "nvidia,tegra114-spi" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(tegra114_spi) = {
|
||||||
|
.name = "tegra114_spi",
|
||||||
|
.id = UCLASS_SPI,
|
||||||
|
.of_match = tegra114_spi_ids,
|
||||||
|
.ops = &tegra114_spi_ops,
|
||||||
|
.ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
|
||||||
|
.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
|
||||||
|
.priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
|
||||||
|
.per_child_auto_alloc_size = sizeof(struct spi_slave),
|
||||||
|
.probe = tegra114_spi_probe,
|
||||||
|
};
|
||||||
|
|
|
@ -7,15 +7,16 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <malloc.h>
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
#include <asm/arch/clock.h>
|
#include <asm/arch/clock.h>
|
||||||
#include <asm/arch/pinmux.h>
|
#include <asm/arch/pinmux.h>
|
||||||
#include <asm/arch-tegra/clk_rst.h>
|
#include <asm/arch-tegra/clk_rst.h>
|
||||||
#include <asm/arch-tegra20/tegra20_sflash.h>
|
|
||||||
#include <spi.h>
|
#include <spi.h>
|
||||||
#include <fdtdec.h>
|
#include <fdtdec.h>
|
||||||
|
#include "tegra_spi.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
@ -64,129 +65,75 @@ struct spi_regs {
|
||||||
u32 rx_fifo; /* SPI_RX_FIFO_0 register */
|
u32 rx_fifo; /* SPI_RX_FIFO_0 register */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_ctrl {
|
struct tegra20_sflash_priv {
|
||||||
struct spi_regs *regs;
|
struct spi_regs *regs;
|
||||||
unsigned int freq;
|
unsigned int freq;
|
||||||
unsigned int mode;
|
unsigned int mode;
|
||||||
int periph_id;
|
int periph_id;
|
||||||
int valid;
|
int valid;
|
||||||
|
int last_transaction_us;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_slave {
|
int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
|
||||||
struct spi_slave slave;
|
struct spi_cs_info *info)
|
||||||
struct tegra_spi_ctrl *ctrl;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* tegra20 only supports one SFLASH controller */
|
|
||||||
static struct tegra_spi_ctrl spi_ctrls[1];
|
|
||||||
|
|
||||||
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
return container_of(slave, struct tegra_spi_slave, slave);
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|
||||||
{
|
{
|
||||||
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
|
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
|
||||||
if (bus != 0 || cs != 0)
|
if (cs != 0)
|
||||||
return 0;
|
return -ENODEV;
|
||||||
else
|
else
|
||||||
return 1;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
|
static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
|
||||||
unsigned int max_hz, unsigned int mode)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi;
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
const void *blob = gd->fdt_blob;
|
||||||
|
int node = bus->of_offset;
|
||||||
|
|
||||||
if (!spi_cs_is_valid(bus, cs)) {
|
plat->base = fdtdec_get_addr(blob, node, "reg");
|
||||||
printf("SPI error: unsupported bus %d / chip select %d\n",
|
plat->periph_id = clock_decode_periph_id(blob, node);
|
||||||
bus, cs);
|
|
||||||
return NULL;
|
if (plat->periph_id == PERIPH_ID_NONE) {
|
||||||
|
debug("%s: could not decode periph id %d\n", __func__,
|
||||||
|
plat->periph_id);
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (max_hz > TEGRA_SPI_MAX_FREQ) {
|
/* Use 500KHz as a suitable default */
|
||||||
printf("SPI error: unsupported frequency %d Hz. Max frequency"
|
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||||
" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
|
500000);
|
||||||
return NULL;
|
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
||||||
|
"spi-deactivate-delay", 0);
|
||||||
|
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
||||||
|
__func__, plat->base, plat->periph_id, plat->frequency,
|
||||||
|
plat->deactivate_delay_us);
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
|
static int tegra20_sflash_probe(struct udevice *bus)
|
||||||
if (!spi) {
|
|
||||||
printf("SPI error: malloc of SPI structure failed\n");
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
spi->ctrl = &spi_ctrls[bus];
|
|
||||||
if (!spi->ctrl) {
|
|
||||||
printf("SPI error: could not find controller for bus %d\n",
|
|
||||||
bus);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (max_hz < spi->ctrl->freq) {
|
|
||||||
debug("%s: limiting frequency from %u to %u\n", __func__,
|
|
||||||
spi->ctrl->freq, max_hz);
|
|
||||||
spi->ctrl->freq = max_hz;
|
|
||||||
}
|
|
||||||
spi->ctrl->mode = mode;
|
|
||||||
|
|
||||||
return &spi->slave;
|
|
||||||
}
|
|
||||||
|
|
||||||
void tegra20_spi_free_slave(struct spi_slave *slave)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
|
||||||
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
free(spi);
|
priv->regs = (struct spi_regs *)plat->base;
|
||||||
|
|
||||||
|
priv->last_transaction_us = timer_get_us();
|
||||||
|
priv->freq = plat->frequency;
|
||||||
|
priv->periph_id = plat->periph_id;
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra20_spi_init(int *node_list, int count)
|
static int tegra20_sflash_claim_bus(struct udevice *bus)
|
||||||
{
|
{
|
||||||
struct tegra_spi_ctrl *ctrl;
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
int i;
|
struct spi_regs *regs = priv->regs;
|
||||||
int node = 0;
|
|
||||||
int found = 0;
|
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
|
||||||
ctrl = &spi_ctrls[i];
|
|
||||||
node = node_list[i];
|
|
||||||
|
|
||||||
ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
|
|
||||||
node, "reg");
|
|
||||||
if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
|
|
||||||
debug("%s: no slink register found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
|
|
||||||
"spi-max-frequency", 0);
|
|
||||||
if (!ctrl->freq) {
|
|
||||||
debug("%s: no slink max frequency found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
|
|
||||||
if (ctrl->periph_id == PERIPH_ID_NONE) {
|
|
||||||
debug("%s: could not decode periph id\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->valid = 1;
|
|
||||||
found = 1;
|
|
||||||
|
|
||||||
debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
|
|
||||||
__func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
|
|
||||||
}
|
|
||||||
return !found;
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra20_spi_claim_bus(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
|
||||||
u32 reg;
|
u32 reg;
|
||||||
|
|
||||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||||
clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
|
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
|
||||||
spi->ctrl->freq);
|
priv->freq);
|
||||||
|
|
||||||
/* Clear stale status here */
|
/* Clear stale status here */
|
||||||
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
|
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
|
||||||
|
@ -197,8 +144,8 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
|
||||||
/*
|
/*
|
||||||
* Use sw-controlled CS, so we can clock in data after ReadID, etc.
|
* Use sw-controlled CS, so we can clock in data after ReadID, etc.
|
||||||
*/
|
*/
|
||||||
reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
|
reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
|
||||||
if (spi->ctrl->mode & 2)
|
if (priv->mode & 2)
|
||||||
reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
|
reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
|
||||||
clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
|
clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
|
||||||
SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
|
SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
|
||||||
|
@ -215,37 +162,54 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra20_spi_cs_activate(struct spi_slave *slave)
|
static void spi_cs_activate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
/* If it's too soon to do another transaction, wait */
|
||||||
|
if (pdata->deactivate_delay_us &&
|
||||||
|
priv->last_transaction_us) {
|
||||||
|
ulong delay_us; /* The delay completed so far */
|
||||||
|
delay_us = timer_get_us() - priv->last_transaction_us;
|
||||||
|
if (delay_us < pdata->deactivate_delay_us)
|
||||||
|
udelay(pdata->deactivate_delay_us - delay_us);
|
||||||
|
}
|
||||||
|
|
||||||
/* CS is negated on Tegra, so drive a 1 to get a 0 */
|
/* CS is negated on Tegra, so drive a 1 to get a 0 */
|
||||||
setbits_le32(®s->command, SPI_CMD_CS_VAL);
|
setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra20_spi_cs_deactivate(struct spi_slave *slave)
|
static void spi_cs_deactivate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
/* CS is negated on Tegra, so drive a 0 to get a 1 */
|
/* CS is negated on Tegra, so drive a 0 to get a 1 */
|
||||||
clrbits_le32(®s->command, SPI_CMD_CS_VAL);
|
clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
|
||||||
|
|
||||||
|
/* Remember time of this transaction so we can honour the bus delay */
|
||||||
|
if (pdata->deactivate_delay_us)
|
||||||
|
priv->last_transaction_us = timer_get_us();
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
|
||||||
const void *data_out, void *data_in, unsigned long flags)
|
const void *data_out, void *data_in,
|
||||||
|
unsigned long flags)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
struct spi_regs *regs = priv->regs;
|
||||||
u32 reg, tmpdout, tmpdin = 0;
|
u32 reg, tmpdout, tmpdin = 0;
|
||||||
const u8 *dout = data_out;
|
const u8 *dout = data_out;
|
||||||
u8 *din = data_in;
|
u8 *din = data_in;
|
||||||
int num_bytes;
|
int num_bytes;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
|
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
|
||||||
slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
|
__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
|
||||||
if (bitlen % 8)
|
if (bitlen % 8)
|
||||||
return -1;
|
return -1;
|
||||||
num_bytes = bitlen / 8;
|
num_bytes = bitlen / 8;
|
||||||
|
@ -262,7 +226,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
|
debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
|
||||||
|
|
||||||
if (flags & SPI_XFER_BEGIN)
|
if (flags & SPI_XFER_BEGIN)
|
||||||
spi_cs_activate(slave);
|
spi_cs_activate(dev);
|
||||||
|
|
||||||
/* handle data in 32-bit chunks */
|
/* handle data in 32-bit chunks */
|
||||||
while (num_bytes > 0) {
|
while (num_bytes > 0) {
|
||||||
|
@ -327,7 +291,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flags & SPI_XFER_END)
|
if (flags & SPI_XFER_END)
|
||||||
spi_cs_deactivate(slave);
|
spi_cs_deactivate(dev);
|
||||||
|
|
||||||
debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
|
debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
|
||||||
tmpdin, readl(®s->status));
|
tmpdin, readl(®s->status));
|
||||||
|
@ -339,3 +303,51 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
|
||||||
|
{
|
||||||
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
if (speed > plat->frequency)
|
||||||
|
speed = plat->frequency;
|
||||||
|
priv->freq = speed;
|
||||||
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
|
||||||
|
{
|
||||||
|
struct tegra20_sflash_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
priv->mode = mode;
|
||||||
|
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_spi_ops tegra20_sflash_ops = {
|
||||||
|
.claim_bus = tegra20_sflash_claim_bus,
|
||||||
|
.xfer = tegra20_sflash_xfer,
|
||||||
|
.set_speed = tegra20_sflash_set_speed,
|
||||||
|
.set_mode = tegra20_sflash_set_mode,
|
||||||
|
.cs_info = tegra20_sflash_cs_info,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id tegra20_sflash_ids[] = {
|
||||||
|
{ .compatible = "nvidia,tegra20-sflash" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(tegra20_sflash) = {
|
||||||
|
.name = "tegra20_sflash",
|
||||||
|
.id = UCLASS_SPI,
|
||||||
|
.of_match = tegra20_sflash_ids,
|
||||||
|
.ops = &tegra20_sflash_ops,
|
||||||
|
.ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
|
||||||
|
.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
|
||||||
|
.priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
|
||||||
|
.per_child_auto_alloc_size = sizeof(struct spi_slave),
|
||||||
|
.probe = tegra20_sflash_probe,
|
||||||
|
};
|
||||||
|
|
|
@ -22,14 +22,13 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <malloc.h>
|
#include <dm.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/gpio.h>
|
|
||||||
#include <asm/arch/clock.h>
|
#include <asm/arch/clock.h>
|
||||||
#include <asm/arch-tegra/clk_rst.h>
|
#include <asm/arch-tegra/clk_rst.h>
|
||||||
#include <asm/arch-tegra20/tegra20_slink.h>
|
|
||||||
#include <spi.h>
|
#include <spi.h>
|
||||||
#include <fdtdec.h>
|
#include <fdtdec.h>
|
||||||
|
#include "tegra_spi.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
@ -87,130 +86,70 @@ struct spi_regs {
|
||||||
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
|
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_ctrl {
|
struct tegra30_spi_priv {
|
||||||
struct spi_regs *regs;
|
struct spi_regs *regs;
|
||||||
unsigned int freq;
|
unsigned int freq;
|
||||||
unsigned int mode;
|
unsigned int mode;
|
||||||
int periph_id;
|
int periph_id;
|
||||||
int valid;
|
int valid;
|
||||||
|
int last_transaction_us;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct tegra_spi_slave {
|
struct tegra_spi_slave {
|
||||||
struct spi_slave slave;
|
struct spi_slave slave;
|
||||||
struct tegra_spi_ctrl *ctrl;
|
struct tegra30_spi_priv *ctrl;
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
|
static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
|
||||||
|
|
||||||
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
|
|
||||||
{
|
{
|
||||||
return container_of(slave, struct tegra_spi_slave, slave);
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
const void *blob = gd->fdt_blob;
|
||||||
|
int node = bus->of_offset;
|
||||||
|
|
||||||
|
plat->base = fdtdec_get_addr(blob, node, "reg");
|
||||||
|
plat->periph_id = clock_decode_periph_id(blob, node);
|
||||||
|
|
||||||
|
if (plat->periph_id == PERIPH_ID_NONE) {
|
||||||
|
debug("%s: could not decode periph id %d\n", __func__,
|
||||||
|
plat->periph_id);
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
/* Use 500KHz as a suitable default */
|
||||||
{
|
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||||
if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
|
500000);
|
||||||
|
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
||||||
|
"spi-deactivate-delay", 0);
|
||||||
|
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
||||||
|
__func__, plat->base, plat->periph_id, plat->frequency,
|
||||||
|
plat->deactivate_delay_us);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
else
|
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
|
static int tegra30_spi_probe(struct udevice *bus)
|
||||||
unsigned int max_hz, unsigned int mode)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi;
|
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
|
||||||
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
|
priv->regs = (struct spi_regs *)plat->base;
|
||||||
bus, cs, max_hz, mode);
|
|
||||||
|
|
||||||
if (!spi_cs_is_valid(bus, cs)) {
|
priv->last_transaction_us = timer_get_us();
|
||||||
printf("SPI error: unsupported bus %d / chip select %d\n",
|
priv->freq = plat->frequency;
|
||||||
bus, cs);
|
priv->periph_id = plat->periph_id;
|
||||||
return NULL;
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (max_hz > TEGRA_SPI_MAX_FREQ) {
|
static int tegra30_spi_claim_bus(struct udevice *bus)
|
||||||
printf("SPI error: unsupported frequency %d Hz. Max frequency"
|
|
||||||
" is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
|
|
||||||
if (!spi) {
|
|
||||||
printf("SPI error: malloc of SPI structure failed\n");
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
spi->ctrl = &spi_ctrls[bus];
|
|
||||||
if (!spi->ctrl) {
|
|
||||||
printf("SPI error: could not find controller for bus %d\n",
|
|
||||||
bus);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (max_hz < spi->ctrl->freq) {
|
|
||||||
debug("%s: limiting frequency from %u to %u\n", __func__,
|
|
||||||
spi->ctrl->freq, max_hz);
|
|
||||||
spi->ctrl->freq = max_hz;
|
|
||||||
}
|
|
||||||
spi->ctrl->mode = mode;
|
|
||||||
|
|
||||||
return &spi->slave;
|
|
||||||
}
|
|
||||||
|
|
||||||
void tegra30_spi_free_slave(struct spi_slave *slave)
|
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
struct spi_regs *regs = priv->regs;
|
||||||
free(spi);
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra30_spi_init(int *node_list, int count)
|
|
||||||
{
|
|
||||||
struct tegra_spi_ctrl *ctrl;
|
|
||||||
int i;
|
|
||||||
int node = 0;
|
|
||||||
int found = 0;
|
|
||||||
|
|
||||||
for (i = 0; i < count; i++) {
|
|
||||||
ctrl = &spi_ctrls[i];
|
|
||||||
node = node_list[i];
|
|
||||||
|
|
||||||
ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
|
|
||||||
node, "reg");
|
|
||||||
if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
|
|
||||||
debug("%s: no slink register found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
|
|
||||||
"spi-max-frequency", 0);
|
|
||||||
if (!ctrl->freq) {
|
|
||||||
debug("%s: no slink max frequency found\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
|
|
||||||
if (ctrl->periph_id == PERIPH_ID_NONE) {
|
|
||||||
debug("%s: could not decode periph id\n", __func__);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
ctrl->valid = 1;
|
|
||||||
found = 1;
|
|
||||||
|
|
||||||
debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
|
|
||||||
__func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
|
|
||||||
}
|
|
||||||
return !found;
|
|
||||||
}
|
|
||||||
|
|
||||||
int tegra30_spi_claim_bus(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
|
||||||
u32 reg;
|
u32 reg;
|
||||||
|
|
||||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||||
clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
|
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
|
||||||
spi->ctrl->freq);
|
priv->freq);
|
||||||
|
|
||||||
/* Clear stale status here */
|
/* Clear stale status here */
|
||||||
reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
|
reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
|
||||||
|
@ -227,29 +166,46 @@ int tegra30_spi_claim_bus(struct spi_slave *slave)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra30_spi_cs_activate(struct spi_slave *slave)
|
static void spi_cs_activate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
/* If it's too soon to do another transaction, wait */
|
||||||
|
if (pdata->deactivate_delay_us &&
|
||||||
|
priv->last_transaction_us) {
|
||||||
|
ulong delay_us; /* The delay completed so far */
|
||||||
|
delay_us = timer_get_us() - priv->last_transaction_us;
|
||||||
|
if (delay_us < pdata->deactivate_delay_us)
|
||||||
|
udelay(pdata->deactivate_delay_us - delay_us);
|
||||||
|
}
|
||||||
|
|
||||||
/* CS is negated on Tegra, so drive a 1 to get a 0 */
|
/* CS is negated on Tegra, so drive a 1 to get a 0 */
|
||||||
setbits_le32(®s->command, SLINK_CMD_CS_VAL);
|
setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra30_spi_cs_deactivate(struct spi_slave *slave)
|
static void spi_cs_deactivate(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
|
||||||
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
/* CS is negated on Tegra, so drive a 0 to get a 1 */
|
/* CS is negated on Tegra, so drive a 0 to get a 1 */
|
||||||
clrbits_le32(®s->command, SLINK_CMD_CS_VAL);
|
clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
|
||||||
|
|
||||||
|
/* Remember time of this transaction so we can honour the bus delay */
|
||||||
|
if (pdata->deactivate_delay_us)
|
||||||
|
priv->last_transaction_us = timer_get_us();
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||||
const void *data_out, void *data_in, unsigned long flags)
|
const void *data_out, void *data_in,
|
||||||
|
unsigned long flags)
|
||||||
{
|
{
|
||||||
struct tegra_spi_slave *spi = to_tegra_spi(slave);
|
struct udevice *bus = dev->parent;
|
||||||
struct spi_regs *regs = spi->ctrl->regs;
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
struct spi_regs *regs = priv->regs;
|
||||||
u32 reg, tmpdout, tmpdin = 0;
|
u32 reg, tmpdout, tmpdin = 0;
|
||||||
const u8 *dout = data_out;
|
const u8 *dout = data_out;
|
||||||
u8 *din = data_in;
|
u8 *din = data_in;
|
||||||
|
@ -257,7 +213,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
|
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
|
||||||
__func__, slave->bus, slave->cs, dout, din, bitlen);
|
__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
|
||||||
if (bitlen % 8)
|
if (bitlen % 8)
|
||||||
return -1;
|
return -1;
|
||||||
num_bytes = bitlen / 8;
|
num_bytes = bitlen / 8;
|
||||||
|
@ -276,11 +232,11 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
|
|
||||||
clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
|
clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
|
||||||
SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
|
SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
|
||||||
(slave->cs << SLINK_CMD2_SS_EN_SHIFT));
|
(spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
|
||||||
debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
|
debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
|
||||||
|
|
||||||
if (flags & SPI_XFER_BEGIN)
|
if (flags & SPI_XFER_BEGIN)
|
||||||
spi_cs_activate(slave);
|
spi_cs_activate(dev);
|
||||||
|
|
||||||
/* handle data in 32-bit chunks */
|
/* handle data in 32-bit chunks */
|
||||||
while (num_bytes > 0) {
|
while (num_bytes > 0) {
|
||||||
|
@ -344,7 +300,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flags & SPI_XFER_END)
|
if (flags & SPI_XFER_END)
|
||||||
spi_cs_deactivate(slave);
|
spi_cs_deactivate(dev);
|
||||||
|
|
||||||
debug("%s: transfer ended. Value=%08x, status = %08x\n",
|
debug("%s: transfer ended. Value=%08x, status = %08x\n",
|
||||||
__func__, tmpdin, readl(®s->status));
|
__func__, tmpdin, readl(®s->status));
|
||||||
|
@ -357,3 +313,54 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
|
||||||
|
{
|
||||||
|
struct tegra_spi_platdata *plat = bus->platdata;
|
||||||
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
if (speed > plat->frequency)
|
||||||
|
speed = plat->frequency;
|
||||||
|
priv->freq = speed;
|
||||||
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
|
||||||
|
{
|
||||||
|
struct tegra30_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
priv->mode = mode;
|
||||||
|
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_spi_ops tegra30_spi_ops = {
|
||||||
|
.claim_bus = tegra30_spi_claim_bus,
|
||||||
|
.xfer = tegra30_spi_xfer,
|
||||||
|
.set_speed = tegra30_spi_set_speed,
|
||||||
|
.set_mode = tegra30_spi_set_mode,
|
||||||
|
/*
|
||||||
|
* cs_info is not needed, since we require all chip selects to be
|
||||||
|
* in the device tree explicitly
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id tegra30_spi_ids[] = {
|
||||||
|
{ .compatible = "nvidia,tegra20-slink" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(tegra30_spi) = {
|
||||||
|
.name = "tegra20_slink",
|
||||||
|
.id = UCLASS_SPI,
|
||||||
|
.of_match = tegra30_spi_ids,
|
||||||
|
.ops = &tegra30_spi_ops,
|
||||||
|
.ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
|
||||||
|
.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
|
||||||
|
.priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
|
||||||
|
.per_child_auto_alloc_size = sizeof(struct spi_slave),
|
||||||
|
.probe = tegra30_spi_probe,
|
||||||
|
};
|
||||||
|
|
12
drivers/spi/tegra_spi.h
Normal file
12
drivers/spi/tegra_spi.h
Normal file
|
@ -0,0 +1,12 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2014 Google, Inc
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
struct tegra_spi_platdata {
|
||||||
|
enum periph_id periph_id;
|
||||||
|
int frequency; /* Default clock frequency, -1 for none */
|
||||||
|
ulong base;
|
||||||
|
uint deactivate_delay_us; /* Delay to wait after deactivate */
|
||||||
|
};
|
|
@ -59,7 +59,7 @@
|
||||||
BOARD_EXTRA_ENV_SETTINGS
|
BOARD_EXTRA_ENV_SETTINGS
|
||||||
|
|
||||||
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
|
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
|
||||||
#define CONFIG_FDT_SPI
|
#define CONFIG_TEGRA_SPI
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* overrides for SPL build here */
|
/* overrides for SPL build here */
|
||||||
|
|
|
@ -24,6 +24,8 @@
|
||||||
#ifndef CONFIG_SPL_BUILD
|
#ifndef CONFIG_SPL_BUILD
|
||||||
#define CONFIG_DM_SERIAL
|
#define CONFIG_DM_SERIAL
|
||||||
#endif
|
#endif
|
||||||
|
#define CONFIG_DM_SPI
|
||||||
|
#define CONFIG_DM_SPI_FLASH
|
||||||
|
|
||||||
#define CONFIG_SYS_TIMER_RATE 1000000
|
#define CONFIG_SYS_TIMER_RATE 1000000
|
||||||
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
|
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
|
||||||
|
|
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