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https://github.com/AsahiLinux/u-boot
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arm: Remove smdk2410 board
This board has not been converted to DM_SERIAL by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: David Müller <d.mueller@elsoft.ch>
This commit is contained in:
Simon Glass
Tom Rini
parent
8ff89f8db8
commit
fd9080ea50
9 changed files with 0 additions and 520 deletions
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@ -152,10 +152,6 @@ config TARGET_VCMA9
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bool "Support VCMA9"
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select CPU_ARM920T
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config TARGET_SMDK2410
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bool "Support smdk2410"
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select CPU_ARM920T
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config TARGET_ASPENITE
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bool "Support aspenite"
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select CPU_ARM926EJS
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@ -1007,7 +1003,6 @@ source "board/olimex/mx23_olinuxino/Kconfig"
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source "board/phytec/pcm051/Kconfig"
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source "board/phytec/pcm052/Kconfig"
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source "board/ppcag/bg0900/Kconfig"
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source "board/samsung/smdk2410/Kconfig"
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source "board/sandisk/sansa_fuze_plus/Kconfig"
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source "board/schulercontrol/sc_sps_1/Kconfig"
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source "board/siemens/draco/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_SMDK2410
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config SYS_BOARD
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default "smdk2410"
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config SYS_VENDOR
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default "samsung"
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config SYS_SOC
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default "s3c24x0"
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config SYS_CONFIG_NAME
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default "smdk2410"
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endif
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@ -1,6 +0,0 @@
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SMDK2410 BOARD
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M: David Müller <d.mueller@elsoft.ch>
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S: Maintained
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F: board/samsung/smdk2410/
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F: include/configs/smdk2410.h
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F: configs/smdk2410_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := smdk2410.o
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obj-y += lowlevel_init.o
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@ -1,146 +0,0 @@
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the Samsung SMDK2410 by
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/* some parameters for the board */
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/*
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*
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* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
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*
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* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
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*
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*/
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#define BWSCON 0x48000000
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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#define DW32 (0x2)
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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#define B1_BWSCON (DW32)
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#define B2_BWSCON (DW16)
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#define B3_BWSCON (DW16 + WAIT + UBLB)
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#define B4_BWSCON (DW16)
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#define B5_BWSCON (DW16)
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#define B6_BWSCON (DW32)
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#define B7_BWSCON (DW32)
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/* BANK0CON */
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#define B0_Tacs 0x0 /* 0clk */
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#define B0_Tcos 0x0 /* 0clk */
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#define B0_Tacc 0x7 /* 14clk */
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#define B0_Tcoh 0x0 /* 0clk */
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#define B0_Tah 0x0 /* 0clk */
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#define B0_Tacp 0x0
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#define B0_PMC 0x0 /* normal */
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/* BANK1CON */
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#define B1_Tacs 0x0 /* 0clk */
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#define B1_Tcos 0x0 /* 0clk */
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#define B1_Tacc 0x7 /* 14clk */
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#define B1_Tcoh 0x0 /* 0clk */
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#define B1_Tah 0x0 /* 0clk */
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#define B1_Tacp 0x0
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#define B1_PMC 0x0
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#define B2_Tacs 0x0
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#define B2_Tcos 0x0
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#define B2_Tacc 0x7
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#define B2_Tcoh 0x0
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#define B2_Tah 0x0
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#define B2_Tacp 0x0
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#define B2_PMC 0x0
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#define B3_Tacs 0x0 /* 0clk */
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#define B3_Tcos 0x3 /* 4clk */
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#define B3_Tacc 0x7 /* 14clk */
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#define B3_Tcoh 0x1 /* 1clk */
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#define B3_Tah 0x0 /* 0clk */
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#define B3_Tacp 0x3 /* 6clk */
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#define B3_PMC 0x0 /* normal */
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#define B4_Tacs 0x0 /* 0clk */
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#define B4_Tcos 0x0 /* 0clk */
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#define B4_Tacc 0x7 /* 14clk */
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#define B4_Tcoh 0x0 /* 0clk */
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#define B4_Tah 0x0 /* 0clk */
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#define B4_Tacp 0x0
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#define B4_PMC 0x0 /* normal */
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#define B5_Tacs 0x0 /* 0clk */
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#define B5_Tcos 0x0 /* 0clk */
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#define B5_Tacc 0x7 /* 14clk */
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#define B5_Tcoh 0x0 /* 0clk */
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#define B5_Tah 0x0 /* 0clk */
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#define B5_Tacp 0x0
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#define B5_PMC 0x0 /* normal */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x1
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#define B6_SCAN 0x1 /* 9bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 3clk */
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#define B7_SCAN 0x1 /* 9bit */
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/* REFRESH parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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#define Trp 0x0 /* 2clk */
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#define Trc 0x3 /* 7clk */
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#define Tchr 0x2 /* 3clk */
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#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
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/**************************************/
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.globl lowlevel_init
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lowlevel_init:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r1, =CONFIG_SYS_TEXT_BASE
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sub r0, r0, r1
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #13*4
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0x32
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.word 0x30
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.word 0x30
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@ -1,139 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002, 2010
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FCLK_SPEED 1
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#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */
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#define M_MDIV 0xA1
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#define M_PDIV 0x3
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#define M_SDIV 0x1
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#endif
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#define USB_CLOCK 1
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#if (USB_CLOCK == 0)
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif (USB_CLOCK == 1)
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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static inline void pll_delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_early_init_f(void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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writel(0xFFFFFF, &clk_power->locktime);
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/* configure MPLL */
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writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
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&clk_power->mpllcon);
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/* some delay between MPLL and UPLL */
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pll_delay(4000);
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/* configure UPLL */
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writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
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&clk_power->upllcon);
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/* some delay between MPLL and UPLL */
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pll_delay(8000);
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/* set up the I/O ports */
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writel(0x007FFFFF, &gpio->gpacon);
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writel(0x00044555, &gpio->gpbcon);
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writel(0x000007FF, &gpio->gpbup);
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writel(0xAAAAAAAA, &gpio->gpccon);
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writel(0x0000FFFF, &gpio->gpcup);
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writel(0xAAAAAAAA, &gpio->gpdcon);
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writel(0x0000FFFF, &gpio->gpdup);
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writel(0xAAAAAAAA, &gpio->gpecon);
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writel(0x0000FFFF, &gpio->gpeup);
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writel(0x000055AA, &gpio->gpfcon);
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writel(0x000000FF, &gpio->gpfup);
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writel(0xFF95FFBA, &gpio->gpgcon);
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writel(0x0000FFFF, &gpio->gpgup);
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writel(0x002AFAAA, &gpio->gphcon);
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writel(0x000007FF, &gpio->gphup);
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return 0;
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}
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int board_init(void)
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{
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/* arch number of SMDK2410-Board */
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gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x30000100;
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icache_enable();
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dcache_enable();
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return 0;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_CS8900
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
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#endif
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return rc;
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}
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#endif
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/*
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* Hardcoded flash setup:
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* Flash 0 is a non-CFI AMD AM29LV800BB flash.
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*/
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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info->portwidth = FLASH_CFI_16BIT;
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info->chipwidth = FLASH_CFI_BY16;
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info->interface = FLASH_CFI_X16;
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return 1;
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}
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@ -1,18 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_SMDK2410=y
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CONFIG_BOOTDELAY=5
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# CONFIG_SYS_STDIO_DEREGISTER is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SMDK2410 # "
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_UBI=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_KEYBOARD=y
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@ -1,180 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Gary Jennejohn <garyj@denx.de>
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* David Mueller <d.mueller@elsoft.ch>
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*
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* Configuation settings for the SAMSUNG SMDK2410 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
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#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
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#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
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#define CONFIG_SYS_CLK_FREQ 12000000
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Hardware drivers
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*/
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#define CONFIG_CS8900 /* we have a CS8900 on-board */
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#define CONFIG_CS8900_BASE 0x19000300
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#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
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/*
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* select serial console configuration
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*/
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#define CONFIG_S3C24X0_SERIAL
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
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/************************************************************
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* USB support (currently only works with D-cache off)
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************************************************************/
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_OHCI_S3C24XX
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#define CONFIG_DOS_PARTITION
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/************************************************************
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* RTC
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************************************************************/
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#define CONFIG_RTC_S3C24X0
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMDLINE_EDITING
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/* autoboot */
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#define CONFIG_BOOT_RETRY_TIME -1
|
||||
#define CONFIG_RESET_TO_RETRY
|
||||
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 10.0.0.110
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x30800000
|
||||
|
||||
/* support additional compression methods */
|
||||
#define CONFIG_BZIP2
|
||||
#define CONFIG_LZO
|
||||
#define CONFIG_LZMA
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_FLASH_CFI_LEGACY
|
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (19)
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
* BZIP2 / LZO / LZMA need a lot of RAM
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
/*
|
||||
* NAND configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_S3C2410
|
||||
#define CONFIG_SYS_S3C2410_NAND_HWECC
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x4E000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_YAFFS2
|
||||
#define CONFIG_RBTREE
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -164,7 +164,6 @@ CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
|
|||
CONFIG_ARCH_RPC
|
||||
CONFIG_ARCH_S3C2440
|
||||
CONFIG_ARCH_SHARK
|
||||
CONFIG_ARCH_SMDK2410
|
||||
CONFIG_ARCH_TEGRA
|
||||
CONFIG_ARCH_USE_BUILTIN_BSWAP
|
||||
CONFIG_ARCH_VERSATILE_PB
|
||||
|
|
@ -4031,7 +4030,6 @@ CONFIG_SMC_B3TIM_VAL
|
|||
CONFIG_SMC_GCTL_VAL
|
||||
CONFIG_SMC_USE_32_BIT
|
||||
CONFIG_SMC_USE_IOFUNCS
|
||||
CONFIG_SMDK2410
|
||||
CONFIG_SMDK5420
|
||||
CONFIG_SMDKC100
|
||||
CONFIG_SMDKV310
|
||||
|
|
|
|||
Loading…
Reference in a new issue