Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 23:24:38 +00:00
Code Issues Projects Releases Packages Wiki Activity

arm: am33xx: Add support for mulitiple PLL input frequencies

Browse source 
am335x supports various sysclk frequencies which can be determined
using sysboot pins. PLLs should be configures based on this
sysclk frequency. Add PLL configurations for all supported
frequencies.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla 2017-05-05 12:59:10 +05:30 committed by Tom Rini
parent 0650798824
commit fbd6295da4
10 changed files with 172 additions and 68 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
arch/arm/include/asm/arch-am33xx/clock.h
View file

@ -12,6 +12,7 @@
#define _CLOCKS_H_
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_TI81XX
#include <asm/arch/clock_ti81xx.h>
@ -103,6 +104,12 @@ extern const struct dpll_regs dpll_mpu_regs;
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;
extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
extern struct cm_wkuppll *const cmwkup;

2
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
View file

@ -26,6 +26,8 @@
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
#define CM_DLL_READYST 0x4
#define NUM_OPPS 6
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;

13
arch/arm/include/asm/arch-am33xx/hardware.h
View file

@ -61,5 +61,18 @@
/* CPSW Config space */
#define CPSW_BASE 0x4A100000
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
#define CTRL_SYSBOOT_15_14_SHIFT 22
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
#define NUM_CRYSTAL_FREQ 0x4
int clk_get(int clk);
#endif /* __AM33XX_HARDWARE_H */

13
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
View file

@ -85,19 +85,6 @@
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
#define CTRL_SYSBOOT_15_14_SHIFT 22
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
#define NUM_CRYSTAL_FREQ 0x4
/* EDMA3 Base Address */
#define EDMA3_BASE 0x49000000

1
arch/arm/include/asm/arch-am33xx/sys_proto.h
View file

@ -46,3 +46,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
void do_board_detect(void);
u32 get_sys_clk_index(void);

2
arch/arm/mach-omap2/am33xx/board.c
View file

@ -242,8 +242,6 @@ int board_early_init_f(void)
*/
__weak void am33xx_spl_board_init(void)
{
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)

89
arch/arm/mach-omap2/am33xx/clock_am33xx.c
View file

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
@ -55,26 +56,94 @@ struct dpll_params dpll_mpu_opp100 = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core_opp100 = {
1000, OSC-1, -1, -1, 10, 8, 4};
const struct dpll_params dpll_mpu = {
MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
50, OSC-1, -1, -1, 1, 1, 1};
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};
const struct dpll_params *get_dpll_mpu_params(void)
const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
{150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
{125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
{625, 11, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 24 MHz */
{25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
{30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
{100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
{125, 2, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 25 MHz */
{24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
{144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */
{32, 0, 1, -1, -1, -1, -1}, /* OPP TB */
{40, 0, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 26 MHz */
{300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
{360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */
{400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
{500, 12, 1, -1, -1, -1, -1} /* OPP NT */
},
};
const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
{125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
{40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
{500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
};
const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
{303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{303, 12, 2, -1, 4, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
{16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
{200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
};
__weak const struct dpll_params *get_dpll_mpu_params(void)
{
return &dpll_mpu;
return &dpll_mpu_opp100;
}
const struct dpll_params *get_dpll_core_params(void)
{
return &dpll_core;
int ind = get_sys_clk_index();
return &dpll_core_1000MHz[ind];
}
const struct dpll_params *get_dpll_per_params(void)
{
return &dpll_per;
int ind = get_sys_clk_index();
return &dpll_per_192MHz[ind];
}
void setup_clocks_for_console(void)

18
arch/arm/mach-omap2/am33xx/sys_info.c
View file

@ -68,6 +68,24 @@ u32 get_sysboot_value(void)
return readl(&cstat->statusreg) & SYSBOOT_MASK;
}
u32 get_sys_clk_index(void)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
u32 ind = readl(&ctrl->statusreg);
#ifdef CONFIG_AM43XX
u32 src;
src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
else /* Value read from SYS BOOT pins */
#endif
return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
CTRL_SYSBOOT_15_14_SHIFT);
}
#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
"1.0",

72
board/ti/am335x/board.c
View file

@ -256,24 +256,62 @@ int spl_start_uboot(void)
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_bone_black = {
400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
return &dpll_ddr3_303MHz[ind];
else if (board_is_bone_lt() || board_is_icev2())
return &dpll_ddr_bone_black;
return &dpll_ddr3_400MHz[ind];
else if (board_is_evm_15_or_later())
return &dpll_ddr_evm_sk;
return &dpll_ddr3_303MHz[ind];
else
return &dpll_ddr;
return &dpll_ddr2_266MHz[ind];
}
static u8 bone_not_connected_to_ac_power(void)
{
if (board_is_bone()) {
uchar pmic_status_reg;
if (tps65217_reg_read(TPS65217_STATUS,
&pmic_status_reg))
return 1;
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
puts("No AC power, switching to default OPP\n");
return 1;
}
}
return 0;
}
const struct dpll_params *get_dpll_mpu_params(void)
{
int ind = get_sys_clk_index();
int freq = am335x_get_efuse_mpu_max_freq(cdev);
if (bone_not_connected_to_ac_power())
freq = MPUPLL_M_600;
if (board_is_bone_lt())
freq = MPUPLL_M_1000;
switch (freq) {
case MPUPLL_M_1000:
return &dpll_mpu_opp[ind][5];
case MPUPLL_M_800:
return &dpll_mpu_opp[ind][4];
case MPUPLL_M_720:
return &dpll_mpu_opp[ind][3];
case MPUPLL_M_600:
return &dpll_mpu_opp[ind][2];
case MPUPLL_M_500:
return &dpll_mpu_opp100;
case MPUPLL_M_300:
return &dpll_mpu_opp[ind][0];
}
return &dpll_mpu_opp[ind][0];
}
static void scale_vcores_bone(int freq)
@ -294,16 +332,8 @@ static void scale_vcores_bone(int freq)
* On Beaglebone White we need to ensure we have AC power
* before increasing the frequency.
*/
if (board_is_bone()) {
uchar pmic_status_reg;
if (tps65217_reg_read(TPS65217_STATUS,
&pmic_status_reg))
return;
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
puts("No AC power, switching to default OPP\n");
if (bone_not_connected_to_ac_power())
freq = MPUPLL_M_600;
}
}
/*
* Override what we have detected since we know if we have

21
board/ti/am43xx/board.c
View file

@ -49,8 +49,6 @@ void do_board_detect(void)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define NUM_OPPS 6
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
@ -317,25 +315,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
return;
}
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either
* read from efuse or sysboot pins.
*/
static u32 get_sys_clk_index(void)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
u32 ind = readl(&ctrl->statusreg), src;
src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
else /* Value read from SYS BOOT pins */
return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
CTRL_SYSBOOT_15_14_SHIFT);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();