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riscv: fix the wrong swap value register

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Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value

Signed-off-by: Brad Kim <brad.kim@semifive.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
Reviewed-by: Leo Liang <ycliang@andestech.com>
This commit is contained in:
Brad Kim 2020-11-13 20:47:51 +09:00 committed by Andes
parent 5a1a8a63be
commit fb33eaa3a2
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/cpu/start.S
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@ -123,7 +123,7 @@ call_board_init_f_0:
* wait for initialization to complete.
*/
la t0, hart_lottery
li s2, 1
li t1, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
#else