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rockchip: rk3036: fix pll config for correct frequency

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There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang 2017-11-30 16:51:19 +08:00 committed by Philipp Tomsich
parent f9cf8cbb9e
commit faa75ad9e6
1 changed files with 3 additions and 2 deletions
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5
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
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@ -34,10 +34,11 @@ struct rk3036_sdram_priv {
struct rk3036_ddr_config ddr_config; struct rk3036_ddr_config ddr_config;
}; };
/* use integer mode, 396MHz dpll setting /*
* use integer mode, dpll output 792MHz and ddr get 396MHz
* refdiv, fbdiv, postdiv1, postdiv2 * refdiv, fbdiv, postdiv1, postdiv2
*/ */
const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
/* 396Mhz ddr timing */ /* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c, const struct rk3036_ddr_timing ddr_timing = {0x18c,