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mips: octeon: Add cvmx-smix-defs.h header file
Import cvmx-smix-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Aaron Williams
Stefan Roese
parent
9505a7cee5
commit
fa84c78f74
1 changed files with 360 additions and 0 deletions
360
arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
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360
arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
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@ -0,0 +1,360 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon smix.
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*/
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#ifndef __CVMX_SMIX_DEFS_H__
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#define __CVMX_SMIX_DEFS_H__
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static inline u64 CVMX_SMIX_CLK(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0001180000001818ull + (offset) * 256;
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0001180000003818ull + (offset) * 128;
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 0x0001180000003818ull + (offset) * 128;
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003818ull + (offset) * 128;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003818ull + (offset) * 128;
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}
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return 0x0001180000003818ull + (offset) * 128;
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}
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static inline u64 CVMX_SMIX_CMD(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0001180000001800ull + (offset) * 256;
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0001180000003800ull + (offset) * 128;
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 0x0001180000003800ull + (offset) * 128;
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003800ull + (offset) * 128;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003800ull + (offset) * 128;
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}
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return 0x0001180000003800ull + (offset) * 128;
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}
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static inline u64 CVMX_SMIX_EN(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0001180000001820ull + (offset) * 256;
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0001180000003820ull + (offset) * 128;
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 0x0001180000003820ull + (offset) * 128;
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003820ull + (offset) * 128;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003820ull + (offset) * 128;
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}
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return 0x0001180000003820ull + (offset) * 128;
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}
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static inline u64 CVMX_SMIX_RD_DAT(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0001180000001810ull + (offset) * 256;
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0001180000003810ull + (offset) * 128;
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 0x0001180000003810ull + (offset) * 128;
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003810ull + (offset) * 128;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003810ull + (offset) * 128;
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}
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return 0x0001180000003810ull + (offset) * 128;
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}
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static inline u64 CVMX_SMIX_WR_DAT(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0001180000001808ull + (offset) * 256;
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0001180000003808ull + (offset) * 128;
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 0x0001180000003808ull + (offset) * 128;
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003808ull + (offset) * 128;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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return 0x0001180000003808ull + (offset) * 128;
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}
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return 0x0001180000003808ull + (offset) * 128;
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}
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/**
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* cvmx_smi#_clk
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*
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* This register determines the SMI timing characteristics.
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* If software wants to change SMI CLK timing parameters ([SAMPLE]/[SAMPLE_HI]), software
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* must delay the SMI_()_CLK CSR write by at least 512 coprocessor-clock cycles after the
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* previous SMI operation is finished.
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*/
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union cvmx_smix_clk {
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u64 u64;
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struct cvmx_smix_clk_s {
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u64 reserved_25_63 : 39;
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u64 mode : 1;
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u64 reserved_21_23 : 3;
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u64 sample_hi : 5;
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u64 sample_mode : 1;
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u64 reserved_14_14 : 1;
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u64 clk_idle : 1;
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u64 preamble : 1;
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u64 sample : 4;
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u64 phase : 8;
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} s;
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struct cvmx_smix_clk_cn30xx {
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u64 reserved_21_63 : 43;
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u64 sample_hi : 5;
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u64 sample_mode : 1;
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u64 reserved_14_14 : 1;
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u64 clk_idle : 1;
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u64 preamble : 1;
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u64 sample : 4;
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u64 phase : 8;
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} cn30xx;
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struct cvmx_smix_clk_cn30xx cn31xx;
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struct cvmx_smix_clk_cn30xx cn38xx;
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struct cvmx_smix_clk_cn30xx cn38xxp2;
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struct cvmx_smix_clk_s cn50xx;
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struct cvmx_smix_clk_s cn52xx;
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struct cvmx_smix_clk_s cn52xxp1;
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struct cvmx_smix_clk_s cn56xx;
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struct cvmx_smix_clk_s cn56xxp1;
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struct cvmx_smix_clk_cn30xx cn58xx;
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struct cvmx_smix_clk_cn30xx cn58xxp1;
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struct cvmx_smix_clk_s cn61xx;
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struct cvmx_smix_clk_s cn63xx;
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struct cvmx_smix_clk_s cn63xxp1;
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struct cvmx_smix_clk_s cn66xx;
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struct cvmx_smix_clk_s cn68xx;
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struct cvmx_smix_clk_s cn68xxp1;
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struct cvmx_smix_clk_s cn70xx;
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struct cvmx_smix_clk_s cn70xxp1;
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struct cvmx_smix_clk_s cn73xx;
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struct cvmx_smix_clk_s cn78xx;
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struct cvmx_smix_clk_s cn78xxp1;
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struct cvmx_smix_clk_s cnf71xx;
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struct cvmx_smix_clk_s cnf75xx;
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};
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typedef union cvmx_smix_clk cvmx_smix_clk_t;
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/**
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* cvmx_smi#_cmd
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*
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* This register forces a read or write command to the PHY. Write operations to this register
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* create SMI transactions. Software will poll (depending on the transaction type).
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*/
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union cvmx_smix_cmd {
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u64 u64;
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struct cvmx_smix_cmd_s {
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u64 reserved_18_63 : 46;
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u64 phy_op : 2;
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u64 reserved_13_15 : 3;
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u64 phy_adr : 5;
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u64 reserved_5_7 : 3;
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u64 reg_adr : 5;
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} s;
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struct cvmx_smix_cmd_cn30xx {
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u64 reserved_17_63 : 47;
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u64 phy_op : 1;
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u64 reserved_13_15 : 3;
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u64 phy_adr : 5;
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u64 reserved_5_7 : 3;
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u64 reg_adr : 5;
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} cn30xx;
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struct cvmx_smix_cmd_cn30xx cn31xx;
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struct cvmx_smix_cmd_cn30xx cn38xx;
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struct cvmx_smix_cmd_cn30xx cn38xxp2;
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struct cvmx_smix_cmd_s cn50xx;
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struct cvmx_smix_cmd_s cn52xx;
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struct cvmx_smix_cmd_s cn52xxp1;
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struct cvmx_smix_cmd_s cn56xx;
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struct cvmx_smix_cmd_s cn56xxp1;
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struct cvmx_smix_cmd_cn30xx cn58xx;
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struct cvmx_smix_cmd_cn30xx cn58xxp1;
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struct cvmx_smix_cmd_s cn61xx;
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struct cvmx_smix_cmd_s cn63xx;
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struct cvmx_smix_cmd_s cn63xxp1;
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struct cvmx_smix_cmd_s cn66xx;
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struct cvmx_smix_cmd_s cn68xx;
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struct cvmx_smix_cmd_s cn68xxp1;
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struct cvmx_smix_cmd_s cn70xx;
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struct cvmx_smix_cmd_s cn70xxp1;
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struct cvmx_smix_cmd_s cn73xx;
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struct cvmx_smix_cmd_s cn78xx;
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struct cvmx_smix_cmd_s cn78xxp1;
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struct cvmx_smix_cmd_s cnf71xx;
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struct cvmx_smix_cmd_s cnf75xx;
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};
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typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
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/**
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* cvmx_smi#_en
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*
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* Enables the SMI interface.
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*
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*/
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union cvmx_smix_en {
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u64 u64;
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struct cvmx_smix_en_s {
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u64 reserved_1_63 : 63;
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u64 en : 1;
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} s;
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struct cvmx_smix_en_s cn30xx;
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struct cvmx_smix_en_s cn31xx;
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struct cvmx_smix_en_s cn38xx;
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struct cvmx_smix_en_s cn38xxp2;
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struct cvmx_smix_en_s cn50xx;
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struct cvmx_smix_en_s cn52xx;
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struct cvmx_smix_en_s cn52xxp1;
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struct cvmx_smix_en_s cn56xx;
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struct cvmx_smix_en_s cn56xxp1;
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struct cvmx_smix_en_s cn58xx;
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struct cvmx_smix_en_s cn58xxp1;
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struct cvmx_smix_en_s cn61xx;
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struct cvmx_smix_en_s cn63xx;
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struct cvmx_smix_en_s cn63xxp1;
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struct cvmx_smix_en_s cn66xx;
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struct cvmx_smix_en_s cn68xx;
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struct cvmx_smix_en_s cn68xxp1;
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struct cvmx_smix_en_s cn70xx;
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struct cvmx_smix_en_s cn70xxp1;
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struct cvmx_smix_en_s cn73xx;
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struct cvmx_smix_en_s cn78xx;
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struct cvmx_smix_en_s cn78xxp1;
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struct cvmx_smix_en_s cnf71xx;
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struct cvmx_smix_en_s cnf75xx;
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};
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typedef union cvmx_smix_en cvmx_smix_en_t;
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/**
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* cvmx_smi#_rd_dat
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*
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* This register contains the data in a read operation.
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*
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*/
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union cvmx_smix_rd_dat {
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u64 u64;
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struct cvmx_smix_rd_dat_s {
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u64 reserved_18_63 : 46;
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u64 pending : 1;
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u64 val : 1;
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u64 dat : 16;
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} s;
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struct cvmx_smix_rd_dat_s cn30xx;
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struct cvmx_smix_rd_dat_s cn31xx;
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struct cvmx_smix_rd_dat_s cn38xx;
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struct cvmx_smix_rd_dat_s cn38xxp2;
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struct cvmx_smix_rd_dat_s cn50xx;
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struct cvmx_smix_rd_dat_s cn52xx;
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struct cvmx_smix_rd_dat_s cn52xxp1;
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struct cvmx_smix_rd_dat_s cn56xx;
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struct cvmx_smix_rd_dat_s cn56xxp1;
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struct cvmx_smix_rd_dat_s cn58xx;
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struct cvmx_smix_rd_dat_s cn58xxp1;
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struct cvmx_smix_rd_dat_s cn61xx;
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struct cvmx_smix_rd_dat_s cn63xx;
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struct cvmx_smix_rd_dat_s cn63xxp1;
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struct cvmx_smix_rd_dat_s cn66xx;
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struct cvmx_smix_rd_dat_s cn68xx;
|
||||||
|
struct cvmx_smix_rd_dat_s cn68xxp1;
|
||||||
|
struct cvmx_smix_rd_dat_s cn70xx;
|
||||||
|
struct cvmx_smix_rd_dat_s cn70xxp1;
|
||||||
|
struct cvmx_smix_rd_dat_s cn73xx;
|
||||||
|
struct cvmx_smix_rd_dat_s cn78xx;
|
||||||
|
struct cvmx_smix_rd_dat_s cn78xxp1;
|
||||||
|
struct cvmx_smix_rd_dat_s cnf71xx;
|
||||||
|
struct cvmx_smix_rd_dat_s cnf75xx;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* cvmx_smi#_wr_dat
|
||||||
|
*
|
||||||
|
* This register provides the data for a write operation.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
union cvmx_smix_wr_dat {
|
||||||
|
u64 u64;
|
||||||
|
struct cvmx_smix_wr_dat_s {
|
||||||
|
u64 reserved_18_63 : 46;
|
||||||
|
u64 pending : 1;
|
||||||
|
u64 val : 1;
|
||||||
|
u64 dat : 16;
|
||||||
|
} s;
|
||||||
|
struct cvmx_smix_wr_dat_s cn30xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn31xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn38xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn38xxp2;
|
||||||
|
struct cvmx_smix_wr_dat_s cn50xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn52xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn52xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn56xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn56xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn58xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn58xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn61xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn63xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn63xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn66xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn68xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn68xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn70xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn70xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cn73xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn78xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cn78xxp1;
|
||||||
|
struct cvmx_smix_wr_dat_s cnf71xx;
|
||||||
|
struct cvmx_smix_wr_dat_s cnf75xx;
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in a new issue