Merge with git://www.denx.de/git/u-boot.git

CREDITS

@@ -147,6 +147,11 @@ N: Daniel Engstr
 E: daniel@omicron.se
 D: x86 port, Support for sc520_cdp board
 
+N: Hayden Fraser
+E: Hayden.Fraser@freescale.com
+D: Support for ColdFire MCF5253
+W: www.freescale.com
+
 N: Dr. Wolfgang Grandegger
 E: wg@denx.de
 D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
@@ -160,6 +165,11 @@ N: Thomas Frieden
 E: ThomasF@hyperion-entertainment.com
 D: Support for AmigaOne
 
+N: Niklaus Giger
+E: niklaus.giger@netstal.com
+D: Support for HCU(x) boards
+W: www.netstal.com
+
 N: Paul Gortmaker
 E: paul.gortmaker@windriver.com
 D: Support for WRS SBC8347/8349 boards
@@ -252,6 +262,10 @@ E: Raghu.Krishnaprasad@fci.com
 D: Support for Adder-II MPC852T evaluation board
 W: http://www.forcecomputers.com
 
+N: Sergey Kubushyn
+E: ksi@koi8.net
+D: Support for various TI DaVinci based boards.
+
 N: Bernhard Kuhn
 E: bkuhn@metrowerks.com
 D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
@@ -274,6 +288,11 @@ E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
+N: TsiChung Liew
+E: Tsi-Chung.Liew@freescale.com
+D: Support for ColdFire MCF523x, MCF532x, MCF5445x
+W: www.freescale.com
+
 N: Leif Lindholm
 E: leif.lindholm@i3micro.com
 D: Support for AMD dbau1550 board.
@@ -288,6 +307,11 @@ N: Raymond Lo
 E: lo@routefree.com
 D: Support for DOS partitions
 
+N: James MacAulay
+E: james.macaulay@amirix.com
+D: Suppport for Amirix AP1000
+W: www.amirix.com
+
 N: Dan Malek
 E: dan@embeddedalley.com
 D: FADSROM, the grandfather of all of this
@@ -363,8 +387,9 @@ D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
 N: Stefan Roese
-E: stefan.roese@esd-electronics.com
+E: sr@denx.de
-D: AMCC PPC401/403/405GP Support; Windows environment support
+D: AMCC PPC4xx Support
+W: http://www.denx.de
 
 N: Erwin Rol
 E: erwin@muffin.org
@@ -398,6 +423,11 @@ N: Art Shipkowski
 E: art@videon-central.com
 D: Support for NetSilicon NS7520
 
+N: Michal Simek
+E: monstr@monstr.eu
+D: Support for Microblaze, ML401, XUPV2P board
+W: www.monstr.eu
+
 N: Yasushi Shoji
 E: yashi@atmark-techno.com
 D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
@@ -411,6 +441,11 @@ E: andrea.scian@dave-tech.it
 D: Port to B2 board
 W: www.dave-tech.it
 
+N: Timur Tabi
+E: timur@freescale.com
+D: Support for MPC8349E-mITX
+W: www.freescale.com
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
@@ -464,18 +499,3 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
-
-N: James MacAulay
-E: james.macaulay@amirix.com
-D: Suppport for Amirix AP1000
-W: www.amirix.com
-
-N: Timur Tabi
-E: timur@freescale.com
-D: Support for MPC8349E-mITX
-W: www.freescale.com
-
-N: Michal Simek
-E: monstr@monstr.eu
-D: Support for Microblaze, ML401, XUPV2P board
-W: www.monstr.eu

MAINTAINERS

@@ -42,6 +42,10 @@ Yuli Barcohen <yuli@arabellasw.com>
 	Rattler			MPC8248
 	ZPC1900			MPC8265
 
+Michael Barkowski <michael.barkowski@freescale.com>
+
+	MPC8323ERDB		MPC8323
+
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
@@ -158,7 +162,12 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 	VOH405			PPC405EP
 	VOM405			PPC405EP
 	WUH405			PPC405EP
-	CMS700                  PPC405EP
+	CMS700			PPC405EP
+
+Niklaus Giger <niklaus.giger@netstal.com>
+
+	HCU4			PPC405GPr
+	HCU5			PPC440EPx
 
 Frank Gottschling <fgottschling@eltec.de>
 
@@ -179,6 +188,10 @@ Howard Gray <mvsensor@matrix-vision.de>
 
 	MVS1			MPC823
 
+Joe Hamman <joe.hamman@embeddedspecialties.com>
+
+	sbc8641d		MPC8641D
+
 Klaus Heydeck <heydeck@kieback-peter.de>
 
 	KUP4K			MPC855
@@ -208,6 +221,10 @@ The LEOX team <team@leox.org>
 
 	ELPT860			MPC860T
 
+Dave Liu <daveliu@freescale.com>
+
+	MPC8360EMDS		MPC8360
+
 Nye Liu <nyet@zumanetworks.com>
 
 	ZUMA			MPC7xx_74xx
@@ -248,6 +265,7 @@ Tolunay Orkun <torkun@nextio.com>
 John Otken <jotken@softadvances.com>
 
 	luan			PPC440SP
+	taihu			PPC405EP
 
 Keith Outwater <Keith_Outwater@mvis.com>
 
@@ -263,6 +281,10 @@ Denis Peter <d.peter@mpl.ch>
 	MIP405			PPC4xx
 	PIP405			PPC4xx
 
+Kim Phillips <kim.phillips@freescale.com>
+
+	MPC8349EMDS		MPC8349
+
 Daniel Poirot <dan.poirot@windriver.com>
 
 	sbc8240			MPC8240
@@ -286,12 +308,14 @@ Stefan Roese <sr@denx.de>
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
+	rainier			PPC440GRx
 	sequoia			PPC440EPx
 	sycamore		PPC405GPr
 	taishan			PPC440GX
 	walnut			PPC405GP
 	yellowstone		PPC440GR
 	yosemite		PPC440EP
+	zeus			PPC405EP
 
 	P3M750			PPC750FX/GX/GL
 
@@ -309,6 +333,11 @@ Peter De Schrijver <p2@mind.be>
 
 	ML2			PPC4xx
 
+Timur Tabi <timur@freescale.com>
+
+	MPC8349E-mITX		MPC8349
+	MPC8349E-mITX-GP	MPC8349
+
 Erik Theisen <etheisen@mindspring.com>
 
 	W7OLMC			PPC4xx
@@ -341,19 +370,6 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
-Timur Tabi <timur@freescale.com>
-
-	MPC8349E-mITX		MPC8349
-	MPC8349E-mITX-GP	MPC8349
-
-Kim Phillips <kim.phillips@freescale.com>
-
-	MPC8349EMDS		MPC8349
-
-Dave Liu <daveliu@freescale.com>
-
-	MPC8360EMDS		MPC8360
-
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -444,6 +460,12 @@ Nishant Kamat <nskamat@ti.com>
 
 	omap1610h2		ARM926EJS
 
+Sergey Kubushyn <ksi@koi8.net>
+
+	DV-EVM			ARM926EJS
+	SONATA			ARM926EJS
+	SCHMOOGIE		ARM926EJS
+
 Prakash Kumar <prakash@embedx.com>
 
 	cerf250			xscale
@@ -589,6 +611,16 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
 
 	r5200			mcf52x2
 
+TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+	M5235EVB		mcf52x2
+	M5329EVB		mcf532x
+	M54455EVB		mcf5445x
+
+Hayden Fraser <Hayden.Fraser@freescale.com>
+
+	M5253EVBE		mcf52x2
+
 #########################################################################
 # AVR32 Systems:							#
 #									#

MAKEALL

@@ -26,124 +26,287 @@ LIST=""
 ## MPC5xx Systems
 #########################################################################
 
-LIST_5xx="	\
+LIST_5xx="		\
-	cmi_mpc5xx							\
+	cmi_mpc5xx	\
 "
 
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
 
-LIST_5xxx="	\
+LIST_5xxx="		\
-	BC3450		cm5200		cpci5200	EVAL5200	\
+	BC3450		\
-	fo300		icecube_5100	icecube_5200	lite5200b	\
+	cm5200		\
-	mcc200		mecp5200	motionpro	o2dnt		\
+	cpci5200	\
-	pf5200		PM520		TB5200		Total5100	\
+	EVAL5200	\
-	Total5200	Total5200_Rev2	TQM5200		TQM5200_B	\
+	fo300		\
-	TQM5200S	v38b						\
+	icecube_5100	\
+	icecube_5200	\
+	lite5200b	\
+	mcc200		\
+	mecp5200	\
+	motionpro	\
+	o2dnt		\
+	pf5200		\
+	PM520		\
+	TB5200		\
+	Total5100	\
+	Total5200	\
+	Total5200_Rev2	\
+	TQM5200		\
+	TQM5200_B	\
+	TQM5200S	\
+	v38b		\
 "
 
 #########################################################################
 ## MPC512x Systems
 #########################################################################
 
-LIST_512x="	\
+LIST_512x="		\
-	ads5121							\
+	ads5121		\
 "
 
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
-LIST_8xx="	\
+LIST_8xx="		\
-	Adder87x	GENIETV		MBX860T		R360MPI		\
+	Adder87x	\
-	AdderII		GTH		MHPC		RBC823		\
+	AdderII		\
-	ADS860		hermes		MPC86xADS	rmu		\
+	ADS860		\
-	AMX860		IAD210		MPC885ADS	RPXClassic	\
+	AMX860		\
-	c2mon		ICU862_100MHz	MVS1		RPXlite		\
+	c2mon		\
-	CCM		IP860		NETPHONE	RPXlite_DW	\
+	CCM		\
-	cogent_mpc8xx	IVML24		NETTA		RRvision	\
+	cogent_mpc8xx	\
-	ELPT860		IVML24_128	NETTA2		SM850		\
+	ELPT860		\
-	EP88x		IVML24_256	NETTA_ISDN	spc1920		\
+	EP88x		\
-	ESTEEM192E	IVMS8		NETVIA		SPD823TS	\
+	ESTEEM192E	\
-	ETX094		IVMS8_128	NETVIA_V2	svm_sc8xx	\
+	ETX094		\
-	FADS823		IVMS8_256	NX823		SXNI855T	\
+	FADS823		\
-	FADS850SAR	KUP4K		pcu_e		TOP860		\
+	FADS850SAR	\
-	FADS860T	KUP4X		QS823		TQM823L		\
+	FADS860T	\
-	FLAGADM		LANTEC		QS850		TQM823L_LCD	\
+	FLAGADM		\
-	FPS850L		lwmon		QS860T		TQM850L		\
+	FPS850L		\
-	GEN860T		MBX		quantum		TQM855L		\
+	GEN860T		\
-	GEN860T_SC					TQM860L		\
+	GEN860T_SC	\
-							TQM885D		\
+	GENIETV		\
-							uc100		\
+	GTH		\
-							v37		\
+	hermes		\
+	IAD210		\
+	ICU862_100MHz	\
+	IP860		\
+	IVML24		\
+	IVML24_128	\
+	IVML24_256	\
+	IVMS8		\
+	IVMS8_128	\
+	IVMS8_256	\
+	KUP4K		\
+	KUP4X		\
+	LANTEC		\
+	lwmon		\
+	MBX		\
+	MBX860T		\
+	MHPC		\
+	MPC86xADS	\
+	MPC885ADS	\
+	MVS1		\
+	NETPHONE	\
+	NETTA		\
+	NETTA2		\
+	NETTA_ISDN	\
+	NETVIA		\
+	NETVIA_V2	\
+	NX823		\
+	pcu_e		\
+	QS823		\
+	QS850		\
+	QS860T		\
+	quantum		\
+	R360MPI		\
+	RBC823		\
+	rmu		\
+	RPXClassic	\
+	RPXlite		\
+	RPXlite_DW	\
+	RRvision	\
+	SM850		\
+	spc1920		\
+	SPD823TS	\
+	svm_sc8xx	\
+	SXNI855T	\
+	TOP860		\
+	TQM823L		\
+	TQM823L_LCD	\
+	TQM850L		\
+	TQM855L		\
+	TQM860L		\
+	TQM885D		\
+	uc100		\
+	v37		\
 "
 
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
 
-LIST_4xx="	\
+LIST_4xx="		\
-	acadia		acadia_nand	ADCIOP		alpr		\
+	acadia		\
-	AP1000		AR405		ASH405		bamboo		\
+	acadia_nand	\
-	bamboo_nand	bubinga		CANBT		CMS700		\
+	ADCIOP		\
-	CPCI2DP		CPCI405		CPCI4052	CPCI405AB	\
+	alpr		\
-	CPCI405DT	CPCI440		CPCIISER4	CRAYL1		\
+	AP1000		\
-	csb272		csb472		DASA_SIM	DP405		\
+	AR405		\
-	DU405		ebony		ERIC		EXBITGEN	\
+	ASH405		\
-	G2000		HH405		HUB405		JSE		\
+	bamboo		\
-	KAREF		katmai		luan		lwmon5		\
+	bamboo_nand	\
-	METROBOX	MIP405		MIP405T		ML2		\
+	bubinga		\
-	ml300		ocotea		OCRTC		ORSG		\
+	CANBT		\
-	p3p440		PCI405		pcs440ep	PIP405		\
+	CMS700		\
-	PLU405		PMC405		PPChameleonEVB	sbc405		\
+	CPCI2DP		\
-	sc3		sequoia		sequoia_nand	taishan		\
+	CPCI405		\
-	VOH405		VOM405		W7OLMC		W7OLMG		\
+	CPCI4052	\
-	walnut		WUH405		XPEDITE1K	yellowstone	\
+	CPCI405AB	\
-	yosemite	yucca						\
+	CPCI405DT	\
+	CPCI440		\
+	CPCIISER4	\
+	CRAYL1		\
+	csb272		\
+	csb472		\
+	DASA_SIM	\
+	DP405		\
+	DU405		\
+	ebony		\
+	ERIC		\
+	EXBITGEN	\
+	G2000		\
+	hcu4		\
+	hcu5		\
+	HH405		\
+	HUB405		\
+	JSE		\
+	KAREF		\
+	katmai		\
+	luan		\
+	lwmon5		\
+	METROBOX	\
+	MIP405		\
+	MIP405T		\
+	ML2		\
+	ml300		\
+	ocotea		\
+	OCRTC		\
+	ORSG		\
+	p3p440		\
+	PCI405		\
+	pcs440ep	\
+	PIP405		\
+	PLU405		\
+	PMC405		\
+	PPChameleonEVB	\
+	rainier		\
+	sbc405		\
+	sc3		\
+	sequoia		\
+	sequoia_nand	\
+	taihu		\
+	taishan		\
+	VOH405		\
+	VOM405		\
+	W7OLMC		\
+	W7OLMG		\
+	walnut		\
+	WUH405		\
+	XPEDITE1K	\
+	yellowstone	\
+	yosemite	\
+	yucca		\
+	zeus		\
 "
 
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
 
-LIST_8220="	\
+LIST_8220="		\
-	Alaska8220	Yukon8220					\
+	Alaska8220	\
+	Yukon8220	\
 "
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
 
-LIST_824x="	\
+LIST_824x="		\
-	A3000		barco		BMW		CPC45		\
+	A3000		\
-	CU824		debris		eXalion		HIDDEN_DRAGON	\
+	barco		\
-			MOUSSE		MUSENKI		MVBLUE		\
+	BMW		\
-	OXC		PN62		Sandpoint8240	Sandpoint8245	\
+	CPC45		\
-	sbc8240		SL8245		utx8245				\
+	CU824		\
+	debris		\
+	eXalion		\
+	HIDDEN_DRAGON	\
+	MOUSSE		\
+	MUSENKI		\
+	MVBLUE		\
+	OXC		\
+	PN62		\
+	Sandpoint8240	\
+	Sandpoint8245	\
+	sbc8240		\
+	SL8245		\
+	utx8245		\
 "
 
 #########################################################################
 ## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################
 
-LIST_8260="	\
+LIST_8260="		\
-	atc		cogent_mpc8260	CPU86		CPU87		\
+	atc		\
-	ep8248		ep8260		ep82xxm		gw8260		\
+	cogent_mpc8260	\
-	hymod		IPHASE4539	ISPAN		MPC8260ADS	\
+	CPU86		\
-	MPC8266ADS	MPC8272ADS	PM826		PM828		\
+	CPU87		\
-	ppmc8260	Rattler8248	RPXsuper	rsdproto	\
+	ep8248		\
-	sacsng		sbc8260		SCM		TQM8260_AC	\
+	ep8260		\
-	TQM8260_AD	TQM8260_AE	ZPC1900				\
+	ep82xxm		\
+	gw8260		\
+	hymod		\
+	IPHASE4539	\
+	ISPAN		\
+	MPC8260ADS	\
+	MPC8266ADS	\
+	MPC8272ADS	\
+	PM826		\
+	PM828		\
+	ppmc8260	\
+	Rattler8248	\
+	RPXsuper	\
+	rsdproto	\
+	sacsng		\
+	sbc8260		\
+	SCM		\
+	TQM8260_AC	\
+	TQM8260_AD	\
+	TQM8260_AE	\
+	ZPC1900		\
 "
 
 #########################################################################
 ## MPC83xx Systems (includes 8349, etc.)
 #########################################################################
 
-LIST_83xx="	\
+LIST_83xx="		\
-	MPC8313ERDB_33	MPC8313ERDB_66	MPC832XEMDS	MPC8349EMDS	\
+	MPC8313ERDB_33	\
-	MPC8349ITX	MPC8349ITXGP	MPC8360EMDS	sbc8349		\
+	MPC8313ERDB_66	\
-	TQM834x								\
+	MPC8323ERDB	\
+	MPC832XEMDS	\
+	MPC8349EMDS	\
+	MPC8349ITX	\
+	MPC8349ITXGP	\
+	MPC8360EMDS	\
+	sbc8349		\
+	TQM834x		\
 "
 
 
@@ -151,123 +314,233 @@ LIST_83xx="	\
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################
 
-LIST_85xx="	\
+LIST_85xx="		\
-	MPC8540ADS	MPC8540EVAL	MPC8541CDS	MPC8544DS	\
+	MPC8540ADS	\
-	MPC8548CDS	MPC8555CDS	MPC8560ADS	MPC8568MDS	\
+	MPC8540EVAL	\
-	PM854		PM856		sbc8540		sbc8560		\
+	MPC8541CDS	\
-	stxgp3		stxssa		TQM8540		TQM8541		\
+	MPC8544DS	\
-	TQM8555		TQM8560						\
+	MPC8548CDS	\
+	MPC8555CDS	\
+	MPC8560ADS	\
+	MPC8568MDS	\
+	PM854		\
+	PM856		\
+	sbc8540		\
+	sbc8560		\
+	stxgp3		\
+	stxssa		\
+	TQM8540		\
+	TQM8541		\
+	TQM8555		\
+	TQM8560		\
 "
 
 #########################################################################
 ## MPC86xx Systems
 #########################################################################
 
-LIST_86xx="	\
+LIST_86xx="		\
-    MPC8641HPCN	\
+	MPC8641HPCN	\
+	sbc8641d	\
 "
 
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 
-LIST_74xx="	\
+LIST_74xx="		\
-	DB64360		DB64460		EVB64260	P3G4		\
+	DB64360		\
-	p3m7448		PCIPPC2		PCIPPC6		ZUMA		\
+	DB64460		\
-	mpc7448hpc2
+	EVB64260	\
+	mpc7448hpc2	\
+	P3G4		\
+	p3m7448		\
+	PCIPPC2		\
+	PCIPPC6		\
+	ZUMA		\
 "
 
-LIST_7xx="	\
+LIST_TSEC="		\
-	BAB7xx		CPCI750		ELPPC		p3m750		\
+	${LIST_85xx}	\
-	ppmc7xx								\
+	${LIST_86xx}	\
+	${LIST_83xx}	\
 "
 
-LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
+LIST_7xx="		\
-	  ${LIST_8xx}				\
+	BAB7xx		\
-	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	CPCI750		\
-	  ${LIST_83xx}				\
+	ELPPC		\
-	  ${LIST_85xx}				\
+	p3m750		\
-	  ${LIST_86xx}				\
+	ppmc7xx		\
-	  ${LIST_4xx}				\
+"
-	  ${LIST_74xx} ${LIST_7xx}"
+
+LIST_ppc="		\
+	${LIST_5xx}	\
+	${LIST_5xxx}	\
+	${LIST_8xx}	\
+	${LIST_8220}	\
+	${LIST_824x}	\
+	${LIST_8260}	\
+	${LIST_83xx}	\
+	${LIST_85xx}	\
+	${LIST_86xx}	\
+	${LIST_4xx}	\
+	${LIST_74xx}	\
+	${LIST_7xx}	\
+"
 
 #########################################################################
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="assabet dnp1110 gcplus lart shannon"
+LIST_SA="		\
+	assabet		\
+	dnp1110		\
+	gcplus		\
+	lart		\
+	shannon		\
+"
 
 #########################################################################
 ## ARM7 Systems
 #########################################################################
 
-LIST_ARM7="	\
+LIST_ARM7="		\
-	armadillo	B2		ep7312		evb4510		\
+	ap7		\
-	impa7		integratorap	ap7		ap720t		\
+	ap720t		\
-	lpc2292sodimm	modnet50	SMN42				\
+	armadillo	\
+	B2		\
+	ep7312		\
+	evb4510		\
+	impa7		\
+	integratorap	\
+	lpc2292sodimm	\
+	modnet50	\
+	SMN42		\
 "
 
 #########################################################################
 ## ARM9 Systems
 #########################################################################
 
-LIST_ARM9="	\
+LIST_ARM9="			\
-	at91rm9200dk	cmc_pu2						\
+	at91rm9200dk		\
-	ap920t		ap922_XA10	ap926ejs	ap946es		\
+	cmc_pu2			\
-	ap966		cp920t		cp922_XA10	cp926ejs	\
+	ap920t			\
-	cp946es		cp966		lpd7a400	mp2usb		\
+	ap922_XA10		\
-	mx1ads		mx1fs2		netstar		omap1510inn	\
+	ap926ejs		\
-	omap1610h2	omap1610inn	omap730p2	sbc2410x	\
+	ap946es			\
-	scb9328		smdk2400	smdk2410	trab		\
+	ap966			\
-	VCMA9		versatile	versatileab	versatilepb	\
+	cp920t			\
-	voiceblue							\
+	cp922_XA10		\
+	cp926ejs		\
+	cp946es			\
+	cp966			\
+	lpd7a400		\
+	mp2usb			\
+	mx1ads			\
+	mx1fs2			\
+	netstar			\
+	omap1510inn		\
+	omap1610h2		\
+	omap1610inn		\
+	omap730p2		\
+	sbc2410x		\
+	scb9328			\
+	smdk2400		\
+	smdk2410		\
+	trab			\
+	VCMA9			\
+	versatile		\
+	versatileab		\
+	versatilepb		\
+	voiceblue		\
+	davinci_dvevm		\
+	davinci_schmoogie	\
+	davinci_sonata		\
 "
 
 #########################################################################
 ## ARM10 Systems
 #########################################################################
-LIST_ARM10="	\
+LIST_ARM10="		\
-	integratorcp	cp1026						\
+	integratorcp	\
+	cp1026		\
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="	\
+LIST_ARM11="		\
-	cp1136		omap2420h4					\
+	cp1136		\
+	omap2420h4	\
 "
 
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="	\
+LIST_pxa="		\
-	adsvix		cerf250		cradle		csb226		\
+	adsvix		\
-	delta		innokom		lubbock		pleb2		\
+	cerf250		\
-	pxa255_idp	wepep250	xaeniax		xm250		\
+	cradle		\
-	xsengine	zylonite					\
+	csb226		\
+	delta		\
+	innokom		\
+	lubbock		\
+	pleb2		\
+	pxa255_idp	\
+	wepep250	\
+	xaeniax		\
+	xm250		\
+	xsengine	\
+	zylonite	\
 "
 
-LIST_ixp="ixdp425	ixdpg425	pdnb3		scpu"
+LIST_ixp="		\
+	ixdp425		\
+	ixdpg425	\
+	pdnb3		\
+	scpu		\
+"
 
 
-LIST_arm="	\
+LIST_arm="		\
-	${LIST_SA}							\
+	${LIST_SA}	\
-	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11}		\
+	${LIST_ARM7}	\
-	${LIST_pxa} ${LIST_ixp}						\
+	${LIST_ARM9}	\
+	${LIST_ARM10}	\
+	${LIST_ARM11}	\
+	${LIST_pxa}	\
+	${LIST_ixp}	\
 "
 
 #########################################################################
 ## MIPS Systems		(default = big endian)
 #########################################################################
 
-LIST_mips4kc="incaip"
+LIST_mips4kc="		\
+	incaip		\
+"
 
-LIST_mips5kc="purple"
+LIST_mips5kc="		\
+	purple		\
+"
 
-LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
+LIST_au1xx0="		\
+	dbau1000	\
+	dbau1100	\
+	dbau1500	\
+	dbau1550	\
+	dbau1550_el	\
+	gth2		\
+"
 
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
+LIST_mips="		\
+	${LIST_mips4kc}	\
+	${LIST_mips5kc}	\
+	${LIST_au1xx0}	\
+"
 
 #########################################################################
 ## MIPS Systems		(little endian)
@@ -277,36 +550,55 @@ LIST_mips4kc_el=""
 
 LIST_mips5kc_el=""
 
-LIST_au1xx0_el="dbau1550_el"
+LIST_au1xx0_el="	\
+	dbau1550_el	\
+"
 
-LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
+LIST_mips_el="			\
+	${LIST_mips4kc_el}	\
+	${LIST_mips5kc_el}	\
+	${LIST_au1xx0_el}	\
+"
 
 #########################################################################
 ## i386 Systems
 #########################################################################
 
-LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
+LIST_I486="		\
+	sc520_cdp	\
+	sc520_spunk	\
+	sc520_spunk_rel	\
+"
 
-LIST_x86="${LIST_I486}"
+LIST_x86="		\
+	${LIST_I486}	\
+"
 
 #########################################################################
 ## NIOS Systems
 #########################################################################
 
-LIST_nios="	\
+LIST_nios="			\
-	ADNPESC1		ADNPESC1_base_32			\
+	ADNPESC1		\
-	ADNPESC1_DNPEVA2_base_32					\
+	ADNPESC1_base_32	\
-	DK1C20			DK1C20_standard_32			\
+	ADNPESC1_DNPEVA2_base_32\
-	DK1S10			DK1S10_standard_32 DK1S10_mtx_ldk_20	\
+	DK1C20			\
+	DK1C20_standard_32	\
+	DK1S10			\
+	DK1S10_standard_32	\
+	DK1S10_mtx_ldk_20	\
 "
 
 #########################################################################
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="	\
+LIST_nios2="		\
-	EP1C20		EP1S10		EP1S40				\
+	EP1C20		\
-	PCI5441		PK1C20						\
+	EP1S10		\
+	EP1S40		\
+	PCI5441		\
+	PK1C20		\
 "
 
 #########################################################################
@@ -314,31 +606,49 @@ LIST_nios2="	\
 #########################################################################
 
 LIST_microblaze="	\
-	suzaku		ml401		xupv2p
+	suzaku		\
+	ml401		\
+	xupv2p		\
 "
 
 #########################################################################
 ## ColdFire Systems
 #########################################################################
 
-LIST_coldfire="	\
+LIST_coldfire="			\
-	cobra5272	EB+MCF-EV123	EB+MCF-EV123_internal		\
+	cobra5272		\
-	idmr		M5271EVB	M5272C3		M5282EVB	\
+	EB+MCF-EV123		\
-	TASREG		r5200		M5271EVB			\
+	EB+MCF-EV123_internal	\
+	idmr			\
+	M5235EVB		\
+	M5249EVB		\
+	M5253EVB		\
+	M5271EVB		\
+	M5272C3			\
+	M5282EVB		\
+	M5329EVB		\
+	M54455EVB		\
+	r5200			\
+	TASREG			\
 "
 
 #########################################################################
 ## AVR32 Systems
 #########################################################################
 
-LIST_avr32="atstk1002"
+LIST_avr32="		\
+	atstk1002	\
+"
 
 #########################################################################
 ## Blackfin Systems
 #########################################################################
 
-LIST_blackfin=" \
+LIST_blackfin="		\
-	bf533-ezkit	bf533-stamp	bf537-stamp	bf561-ezkit	\
+	bf533-ezkit	\
+	bf533-stamp	\
+	bf537-stamp	\
+	bf561-ezkit	\
 "
 
 #-----------------------------------------------------------------------
@@ -375,7 +685,7 @@ do
 	mips|mips_el| \
 	nios|nios2| \
 	ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
-	x86|I486)
+	x86|I486|TSEC)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}

Makefile

@@ -22,9 +22,9 @@
 #
 
 VERSION = 1
-PATCHLEVEL = 2
+PATCHLEVEL = 3
 SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -34,6 +34,7 @@ HOSTARCH := $(shell uname -m | \
 	    -e s/arm.*/arm/ \
 	    -e s/sa110/arm/ \
 	    -e s/powerpc/ppc/ \
+	    -e s/ppc64/ppc/ \
 	    -e s/macppc/ppc/)
 
 HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
@@ -189,6 +190,8 @@ endif
 OBJS := $(addprefix $(obj),$(OBJS))
 
 LIBS  = lib_generic/libgeneric.a
+LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
+	"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 ifdef SOC
@@ -208,9 +211,14 @@ LIBS += drivers/libdrivers.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/net/libnet.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
 endif
+ifeq ($(CPU),mpc85xx)
+LIBS += drivers/qe/qe.a
+endif
+LIBS += drivers/serial/libserial.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/drivers/libpostdrivers.a
 LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
@@ -1138,6 +1146,12 @@ EXBITGEN_config:	unconfig
 G2000_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
 
+hcu4_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
+
+hcu5_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
+
 HH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
 
@@ -1257,6 +1271,9 @@ rainier_nand_config: unconfig
 sc3_config:unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
 
+taihu_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
+
 taishan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
 
@@ -1294,6 +1311,9 @@ yellowstone_config: unconfig
 yucca_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
 
+zeus_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
+
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
@@ -1621,6 +1641,31 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
+M5235EVB_config \
+M5235EVB_Flash16_config \
+M5235EVB_Flash32_config:	unconfig
+	@case "$@" in \
+	M5235EVB_config)		FLASH=16;; \
+	M5235EVB_Flash16_config)	FLASH=16;; \
+	M5235EVB_Flash32_config)	FLASH=32;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${FLASH}" != "16" ] ; then \
+		echo "#define NORFLASH_PS32BIT	1" >> include/config.h ; \
+		echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+		cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \
+	else \
+		echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \
+		cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \
+	fi
+	@$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale
+
+M5249EVB_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
+
+M5253EVBE_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
+
 cobra5272_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
 
@@ -1656,6 +1701,46 @@ TASREG_config :		unconfig
 r5200_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
 
+M5329AFEE_config \
+M5329BFEE_config :	unconfig
+	@case "$@" in \
+	M5329AFEE_config)	NAND=0;; \
+	M5329BFEE_config)	NAND=16;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${NAND}" != "0" ] ; then \
+		echo "#define NANDFLASH_SIZE	$${NAND}" > $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
+
+M54455EVB_config \
+M54455EVB_atmel_config \
+M54455EVB_intel_config \
+M54455EVB_a33_config \
+M54455EVB_a66_config \
+M54455EVB_i33_config \
+M54455EVB_i66_config :	unconfig
+	@case "$@" in \
+	M54455EVB_config)		FLASH=ATMEL; FREQ=33333333;; \
+	M54455EVB_atmel_config)		FLASH=ATMEL; FREQ=33333333;; \
+	M54455EVB_intel_config)		FLASH=INTEL; FREQ=33333333;; \
+	M54455EVB_a33_config)		FLASH=ATMEL; FREQ=33333333;; \
+	M54455EVB_a66_config)		FLASH=ATMEL; FREQ=66666666;; \
+	M54455EVB_i33_config)		FLASH=INTEL; FREQ=33333333;; \
+	M54455EVB_i66_config)		FLASH=INTEL; FREQ=66666666;; \
+	esac; \
+	>include/config.h ; \
+	if [ "$${FLASH}" == "INTEL" ] ; then \
+		echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+		echo "... with INTEL boot..." ; \
+	else \
+		echo "#define CFG_ATMEL_BOOT"	>> $(obj)include/config.h ; \
+		echo "... with ATMEL boot..." ; \
+	fi; \
+	echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
+	echo "... with $${FREQ}Hz input clock"
+	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
+
 #########################################################################
 ## MPC83xx Systems
 #########################################################################
@@ -1665,14 +1750,17 @@ MPC8313ERDB_66_config: unconfig
 	@mkdir -p $(obj)include
 	@echo "" >$(obj)include/config.h ; \
 	if [ "$(findstring _33_,$@)" ] ; then \
-		echo "...33M ..." ; \
+		echo -n "...33M ..." ; \
 		echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _66_,$@)" ] ; then \
-		echo "...66M..." ; \
+		echo -n "...66M..." ; \
 		echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+
+MPC8323ERDB_config:	unconfig
+	@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
 
 MPC832XEMDS_config \
 MPC832XEMDS_HOST_33_config \
@@ -1681,7 +1769,7 @@ MPC832XEMDS_SLAVE_config:	unconfig
 	@mkdir -p $(obj)include
 	@echo "" >$(obj)include/config.h ; \
 	if [ "$(findstring _HOST_,$@)" ] ; then \
-		echo "... PCI HOST " ; \
+		echo -n "... PCI HOST " ; \
 		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _SLAVE_,$@)" ] ; then \
@@ -1690,31 +1778,31 @@ MPC832XEMDS_SLAVE_config:	unconfig
 		echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _33_,$@)" ] ; then \
-		echo "...33M ..." ; \
+		echo -n "...33M ..." ; \
 		echo "#define PCI_33M" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _66_,$@)" ] ; then \
-		echo "...66M..." ; \
+		echo -n "...66M..." ; \
 		echo "#define PCI_66M" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
+	@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
 
 MPC8349EMDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
 
 MPC8349ITX_config \
 MPC8349ITX_LOWBOOT_config \
 MPC8349ITXGP_config:	unconfig
 	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/mpc8349itx
+	@mkdir -p $(obj)board/freescale/mpc8349itx
 	@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
 	@if [ "$(findstring GP,$@)" ] ; then \
-		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
 	fi
 	@if [ "$(findstring LOWBOOT,$@)" ] ; then \
-		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
 	fi
-	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
+	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
 
 MPC8360EMDS_config \
 MPC8360EMDS_HOST_33_config \
@@ -1723,7 +1811,7 @@ MPC8360EMDS_SLAVE_config:	unconfig
 	@mkdir -p $(obj)include
 	@echo "" >$(obj)include/config.h ; \
 	if [ "$(findstring _HOST_,$@)" ] ; then \
-		echo "... PCI HOST " ; \
+		echo -n "... PCI HOST " ; \
 		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _SLAVE_,$@)" ] ; then \
@@ -1732,14 +1820,14 @@ MPC8360EMDS_SLAVE_config:	unconfig
 		echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _33_,$@)" ] ; then \
-		echo "...33M ..." ; \
+		echo -n "...33M ..." ; \
 		echo "#define PCI_33M" >>$(obj)include/config.h ; \
 	fi ; \
 	if [ "$(findstring _66_,$@)" ] ; then \
-		echo "...66M..." ; \
+		echo -n "...66M..." ; \
 		echo "#define PCI_66M" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
+	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
 
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
@@ -1779,17 +1867,38 @@ MPC8540EVAL_66_slave_config:      unconfig
 MPC8560ADS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
 
+MPC8541CDS_legacy_config \
 MPC8541CDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
+	@mkdir -p $(obj)include
+	@echo "" >$(obj)include/config.h ; \
+	if [ "$(findstring _legacy_,$@)" ] ; then \
+		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+		echo "... legacy" ; \
+	fi
+	@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
 
 MPC8544DS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
 
+MPC8548CDS_legacy_config \
 MPC8548CDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
+	@mkdir -p $(obj)include
+	@echo "" >$(obj)include/config.h ; \
+	if [ "$(findstring _legacy_,$@)" ] ; then \
+		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+		echo "... legacy" ; \
+	fi
+	@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
 
+MPC8555CDS_legacy_config \
 MPC8555CDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
+	@mkdir -p $(obj)include
+	@echo "" >$(obj)include/config.h ; \
+	if [ "$(findstring _legacy_,$@)" ] ; then \
+		echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+		echo "... legacy" ; \
+	fi
+	@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
 
 MPC8568MDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
@@ -1860,8 +1969,10 @@ TQM8560_config:		unconfig
 #########################################################################
 
 MPC8641HPCN_config:    unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn
+	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
 
+sbc8641d_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
 
 #########################################################################
 ## 74xx/7xx Systems
@@ -2017,6 +2128,15 @@ omap1510inn_config :	unconfig
 omap5912osk_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap
 
+davinci_dvevm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci
+
+davinci_schmoogie_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
+
+davinci_sonata_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
+
 omap1610inn_config \
 omap1610inn_cs0boot_config \
 omap1610inn_cs3boot_config \
@@ -2214,6 +2334,9 @@ scpu_config:    unconfig
 pxa255_idp_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
 
+trizepsiv_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
+
 wepep250_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa wepep250
 

README

@@ -136,6 +136,8 @@ Directory Hierarchy:
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
+  - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
+  - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
   - mips	Files specific to MIPS CPUs
   - mpc5xx	Files specific to Freescale MPC5xx  CPUs
   - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
@@ -228,114 +230,9 @@ build a config tool - later.
 
 The following options need to be configured:
 
-- CPU Type:	Define exactly one of
+- CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 
-		PowerPC based CPUs:
+- Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
-		-------------------
-		CONFIG_MPC823,	CONFIG_MPC850,	CONFIG_MPC855,	CONFIG_MPC860
-	or	CONFIG_MPC5xx
-	or	CONFIG_MPC8220
-	or	CONFIG_MPC824X, CONFIG_MPC8260
-	or	CONFIG_MPC85xx
-	or	CONFIG_IOP480
-	or	CONFIG_405GP
-	or	CONFIG_405EP
-	or	CONFIG_440
-	or	CONFIG_MPC74xx
-	or	CONFIG_750FX
-
-		ARM based CPUs:
-		---------------
-		CONFIG_SA1110
-		CONFIG_ARM7
-		CONFIG_PXA250
-		CONFIG_PXA27X
-		CONFIG_CPU_MONAHANS
-
-		MicroBlaze based CPUs:
-		----------------------
-		CONFIG_MICROBLAZE
-
-		Nios-2 based CPUs:
-		----------------------
-		CONFIG_NIOS2
-
-		AVR32 based CPUs:
-		----------------------
-		CONFIG_AT32AP
-
-- Board Type:	Define exactly one of
-
-		PowerPC based boards:
-		---------------------
-
-		CONFIG_ADCIOP		CONFIG_FPS860L		CONFIG_OXC
-		CONFIG_ADS860		CONFIG_GEN860T		CONFIG_PCI405
-		CONFIG_AMX860		CONFIG_GENIETV		CONFIG_PCIPPC2
-		CONFIG_AP1000		CONFIG_GTH		CONFIG_PCIPPC6
-		CONFIG_AR405		CONFIG_gw8260		CONFIG_pcu_e
-		CONFIG_BAB7xx		CONFIG_hermes		CONFIG_PIP405
-		CONFIG_BC3450		CONFIG_hymod		CONFIG_PM826
-		CONFIG_c2mon		CONFIG_IAD210		CONFIG_ppmc8260
-		CONFIG_CANBT		CONFIG_ICU862		CONFIG_QS823
-		CONFIG_CCM		CONFIG_IP860		CONFIG_QS850
-		CONFIG_CMI		CONFIG_IPHASE4539	CONFIG_QS860T
-		CONFIG_cogent_mpc8260	CONFIG_IVML24		CONFIG_RBC823
-		CONFIG_cogent_mpc8xx	CONFIG_IVML24_128	CONFIG_RPXClassic
-		CONFIG_CPCI405		CONFIG_IVML24_256	CONFIG_RPXlite
-		CONFIG_CPCI4052		CONFIG_IVMS8		CONFIG_RPXsuper
-		CONFIG_CPCIISER4	CONFIG_IVMS8_128	CONFIG_rsdproto
-		CONFIG_CPU86		CONFIG_IVMS8_256	CONFIG_sacsng
-		CONFIG_CRAYL1		CONFIG_JSE		CONFIG_Sandpoint8240
-		CONFIG_CSB272		CONFIG_LANTEC		CONFIG_Sandpoint8245
-		CONFIG_CU824		CONFIG_LITE5200B	CONFIG_sbc8260
-		CONFIG_DASA_SIM		CONFIG_lwmon		CONFIG_sbc8560
-		CONFIG_DB64360		CONFIG_MBX		CONFIG_SM850
-		CONFIG_DB64460		CONFIG_MBX860T		CONFIG_SPD823TS
-		CONFIG_DU405		CONFIG_MHPC		CONFIG_STXGP3
-		CONFIG_DUET_ADS		CONFIG_MIP405		CONFIG_SXNI855T
-		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_TQM823L
-		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM8260
-		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM850L
-		CONFIG_ep8260		CONFIG_MPC8540EVAL	CONFIG_TQM855L
-		CONFIG_ERIC		CONFIG_MPC8560ADS	CONFIG_TQM860L
-		CONFIG_ESTEEM192E	CONFIG_MUSENKI		CONFIG_TTTech
-		CONFIG_ETX094		CONFIG_MVS1		CONFIG_UTX8245
-		CONFIG_EVB64260		CONFIG_NETPHONE		CONFIG_V37
-		CONFIG_FADS823		CONFIG_NETTA		CONFIG_W7OLMC
-		CONFIG_FADS850SAR	CONFIG_NETVIA		CONFIG_W7OLMG
-		CONFIG_FADS860T		CONFIG_NX823		CONFIG_WALNUT
-		CONFIG_FLAGADM		CONFIG_OCRTC		CONFIG_ZPC1900
-		CONFIG_FPS850L		CONFIG_ORSG		CONFIG_ZUMA
-
-		ARM based boards:
-		-----------------
-
-		CONFIG_ARMADILLO,	CONFIG_AT91RM9200DK,	CONFIG_CERF250,
-		CONFIG_CSB637,		CONFIG_DELTA,		CONFIG_DNP1110,
-		CONFIG_EP7312,		CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,
-		CONFIG_IMPA7,	    CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610,
-		CONFIG_KB9202,		CONFIG_LART,		CONFIG_LPD7A400,
-		CONFIG_LUBBOCK,		CONFIG_OSK_OMAP5912,	CONFIG_OMAP2420H4,
-		CONFIG_PLEB2,		CONFIG_SHANNON,		CONFIG_P2_OMAP730,
-		CONFIG_SMDK2400,	CONFIG_SMDK2410,	CONFIG_TRAB,
-		CONFIG_VCMA9
-
-		MicroBlaze based boards:
-		------------------------
-
-		CONFIG_SUZAKU
-
-		Nios-2 based boards:
-		------------------------
-
-		CONFIG_PCI5441 CONFIG_PK1C20
-		CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
-
-		AVR32 based boards:
-		-------------------
-
-		CONFIG_ATSTK1000
 
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one of
@@ -441,7 +338,7 @@ The following options need to be configured:
 		CONFIG_OF_LIBFDT
 		 * New libfdt-based support
 		 * Adds the "fdt" command
-		 * The bootm command does _not_ modify the fdt
+		 * The bootm command automatically updates the fdt
 
 		CONFIG_OF_FLAT_TREE
 		 * Deprecated, see CONFIG_OF_LIBFDT
@@ -450,15 +347,13 @@ The following options need to be configured:
 		 * The environment variable "disable_of", when set,
 		     disables this functionality.
 
-		CONFIG_OF_FLAT_TREE_MAX_SIZE
-
-		The maximum size of the constructed OF tree.
-
 		OF_CPU - The proper name of the cpus node.
 		OF_SOC - The proper name of the soc node.
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 
+		boards with QUICC Engines require OF_QE to set UCC mac addresses
+
 		CONFIG_OF_HAS_BD_T
 
 		 * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
@@ -468,7 +363,7 @@ The following options need to be configured:
 
 		CONFIG_OF_HAS_UBOOT_ENV
 
-		 * CONFIG_OF_LIBFDT - enables the "fdt bd_t" command
+		 * CONFIG_OF_LIBFDT - enables the "fdt env" command
 		 * CONFIG_OF_FLAT_TREE - The resulting flat device tree
 		     will have a copy of u-boot's environment variables
 
@@ -1171,6 +1066,16 @@ The following options need to be configured:
 		Defines a default value for theIP address of a TFTP
 		server to contact when using the "tftboot" command.
 
+- Multicast TFTP Mode:
+		CONFIG_MCAST_TFTP
+
+		Defines whether you want to support multicast TFTP as per
+		rfc-2090; for example to work with atftp.  Lets lots of targets
+		tftp down the same boot image concurrently.  Note: the ethernet
+		driver in use must provide a function: mcast() to join/leave a
+		multicast group.
+
+		CONFIG_BOOTP_RANDOM_DELAY
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 
@@ -1207,6 +1112,9 @@ The following options need to be configured:
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
 
+		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
+		environment variable, not the BOOTP server.
+
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
@@ -1219,7 +1127,7 @@ The following options need to be configured:
 		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
 		to do a dynamic update of a DNS server. To do this, they
 		need the hostname of the DHCP requester.
-		If CONFIG_BOOP_SEND_HOSTNAME is defined, the content
+		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
 		of the "hostname" environment variable is passed as
 		option 12 to the DHCP server.
 
@@ -2492,34 +2400,7 @@ is done by typing:
 	make NAME_config
 
 where "NAME_config" is the name of one of the existing
-configurations; the following names are supported:
+configurations; see the main Makefile for supported names.
-
-	ADCIOP_config		FPS860L_config		omap730p2_config
-	ADS860_config		GEN860T_config		pcu_e_config
-	Alaska8220_config
-	AR405_config		GENIETV_config		PIP405_config
-	at91rm9200dk_config	GTH_config		QS823_config
-	CANBT_config		hermes_config		QS850_config
-	cmi_mpc5xx_config	hymod_config		QS860T_config
-	cogent_common_config	IP860_config		RPXlite_config
-	cogent_mpc8260_config	IVML24_config		RPXlite_DW_config
-	cogent_mpc8xx_config	IVMS8_config		RPXsuper_config
-	CPCI405_config		JSE_config		rsdproto_config
-	CPCIISER4_config	LANTEC_config		Sandpoint8240_config
-	csb272_config		lwmon_config		sbc8260_config
-	CU824_config		MBX860T_config		sbc8560_33_config
-	DUET_ADS_config		MBX_config		sbc8560_66_config
-	EBONY_config		mpc7448hpc2_config	SM850_config
-	ELPT860_config		MPC8260ADS_config	SPD823TS_config
-	ESTEEM192E_config	MPC8540ADS_config	stxgp3_config
-	ETX094_config		MPC8540EVAL_config	SXNI855T_config
-	FADS823_config		NMPC8560ADS_config	TQM823L_config
-	FADS850SAR_config	NETVIA_config		TQM850L_config
-	FADS860T_config		omap1510inn_config	TQM855L_config
-	FPS850L_config		omap1610h2_config	TQM860L_config
-				omap1610inn_config	walnut_config
-				omap5912osk_config	Yukon8220_config
-				omap2420h4_config	ZPC1900_config
 
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for

board/BuS/EB+MCF-EV123/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o
+COBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/BuS/EB+MCF-EV123/mii.c

@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	if (setclear) {
+		MCFGPIO_PASPAR |= 0x0F00;
+		MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+	} else {
+		MCFGPIO_PASPAR &= 0xF0FF;
+		MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_AMD79C874VC	0x0022561B	/* AMD 79C874 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_AMD79C874VC	"AMD79C874VC"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+	volatile fec_t *fecp = (fec_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	volatile fec_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fec_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_s *info = dev->priv;
+	int phyaddr, pass;
+	uint phyno, phytype;
+
+	if (info->phyname_init)
+		return info->phy_addr;
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_AMD79C874VC:
+					strcpy(info->phy_name,
+					       STR_ID_AMD79C874VC);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_AMD79C874VC:
+					printf(STR_ID_AMD79C874VC);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+	volatile fec_t *fecp;
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fec_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

board/ads5121/ads5121.c

@@ -85,9 +85,7 @@ long int initdram (int board_type)
 {
 	u32 msize = 0;
 
-	puts ("Initializing\n");
 	msize = fixed_sdram ();
-	puts ("   DDR RAM: ");
 
 	return msize;
 }

board/ads5121/u-boot.lds

@@ -51,7 +51,6 @@ SECTIONS
   {
     cpu/mpc512x/start.o	(.text)
     *(.text)
-    *(.fixup)
     *(.got1)
     . = ALIGN(16);
     *(.rodata)

board/amcc/bamboo/bamboo.c

@@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
 
-unsigned char cfg_simulate_spd_eeprom[128];
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ *	13 row add bits, 10 column add bits (but 12 row used only).
+ *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ *	12 row add bits, 10 column add bits.
+ *	Prepare a subset (only the used ones) of SPD data
+ *
+ *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ *	the corresponding bank is divided by 2 due to number of Row addresses
+ *	12 in the ECC module
+ *
+ *  Assumes:	64 MB, ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+	0x80,    /* number of SPD bytes used: 128 */
+	0x08,    /*  total number bytes in SPD device = 256 */
+	0x07,    /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+	0x0C,    /* num Row Addr: 12 */
+#else
+	0x0D,    /* num Row Addr: 13 */
+#endif
+	0x09,    /* numColAddr: 9  */
+	0x01,    /* numBanks: 1 */
+	0x20,    /* Module data width: 32 bits */
+	0x00,    /* Module data width continued: +0 */
+	0x04,    /* 2.5 Volt */
+	0x75,    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+#ifdef CONFIG_DDR_ECC
+	0x02,    /* ECC ON : 02 OFF : 00 */
+#else
+	0x00,    /* ECC ON : 02 OFF : 00 */
+#endif
+	0x82,    /* refresh Rate Type: Normal (15.625us) + Self refresh */
+	0,
+	0,
+	0,
+	0x01,    /* wcsbc = 1 */
+	0,
+	0,
+	0x0C,    /* casBit (2,2.5) */
+	0,
+	0,
+	0x00,    /* not registered: 0  registered : 0x02*/
+	0,
+	0xA0,    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+	0,
+	0x00,    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+	0,
+	0x50,    /* tRpNs = 20 ns  */
+	0,
+	0x50,    /* tRcdNs = 20 ns */
+	45,      /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+	0x08,    /* bankSizeID: 32MB */
+#else
+	0x10,    /* bankSizeID: 64MB */
+#endif
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0
+};
+#endif
 
-gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 #if 0
 {	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
     {
@@ -291,73 +452,12 @@ int checkboard(void)
 	return (0);
 }
 
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
-/*************************************************************************
- *
- * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- *	13 row add bits, 10 column add bits (but 12 row used only).
- *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- *	12 row add bits, 10 column add bits.
- *	Prepare a subset (only the used ones) of SPD data
- *
- *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- *	the corresponding bank is divided by 2 due to number of Row addresses
- *	12 in the ECC module
- *
- *  Assumes:	64 MB, ECC, non-registered
- *		PLB @ 133 MHz
- *
- ************************************************************************/
-static void init_spd_array(void)
-{
-	cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
-	cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
-
-#ifdef CONFIG_DDR_ECC
-	cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
-	cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
-	cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
-#else
-	cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
-	cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
-	cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
-#endif
-
-	cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
-	cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
-	cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
-	cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
-	cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
-	cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
-	cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
-	cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
-	cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
-	cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
-
-	cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
-
-	cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
-
-	cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
-	cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
-	cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
-	cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
-}
-#endif
 
 long int initdram (int board_type)
 {
 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 	long dram_size;
 
-	/*
-	 * First write simulated values in eeprom array for onboard bank 0
-	 */
-	init_spd_array();
-
 	dram_size = spd_sdram();
 
 	return dram_size;
@@ -371,11 +471,12 @@ int testdram(void)
 {
 	unsigned long *mem = (unsigned long *)0;
 	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
+	unsigned long k, n, *p32, ctr;
+	const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
 
 	mtmsr(0);
 
-	for (k = 0; k < CFG_KBYTES_SDRAM;
+	for (k = 0; k <	CFG_MBYTES_SDRAM*1024;
 	     ++k, mem += (1024 / sizeof(unsigned long))) {
 		if ((k & 1023) == 0) {
 			printf("%3d MB\r", k / 1024);
@@ -399,6 +500,34 @@ int testdram(void)
 			}
 		}
 	}
+
+	/*
+	 * Perform a sequence test to ensure that all
+	 * memory locations are uniquely addressable
+	 */
+	ctr = 0;
+	p32 = 0;
+	while ((unsigned long)p32 != bend) {
+		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+			printf("Writing	%3d MB\r", (unsigned long)p32 >> 20);
+		*p32++ = ctr++;
+	}
+
+	ctr = 0;
+	p32 = 0;
+	while ((unsigned long)p32 != bend) {
+		if (0 == ((unsigned long)p32 & ((1<<20)-1)))
+			printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
+
+		if (*p32 != ctr) {
+			printf("SDRAM test fails at: %08x\n", p32);
+			return 1;
+		}
+
+		ctr++;
+		p32++;
+	}
+
 	printf("SDRAM test passes\n");
 	return 0;
 }
@@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config)
 /*----------------------------------------------------------------------------+
   | init_default_gpio
   +----------------------------------------------------------------------------*/
-void init_default_gpio(void)
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	int i;
 
@@ -1281,7 +1410,7 @@ void init_default_gpio(void)
   |
   +----------------------------------------------------------------------------*/
 
-void update_uart_ios(uart_config_nb_t uart_config)
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	switch (uart_config)
 	{
@@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config)
 /*----------------------------------------------------------------------------+
   | update_ndfc_ios(void).
   +----------------------------------------------------------------------------*/
-void update_ndfc_ios(void)
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	/* Update GPIO Configuration Table */
 	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
@@ -1427,7 +1556,7 @@ void update_ndfc_ios(void)
 /*----------------------------------------------------------------------------+
   | update_zii_ios(void).
   +----------------------------------------------------------------------------*/
-void update_zii_ios(void)
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	/* Update GPIO Configuration Table */
 	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
@@ -1477,7 +1606,7 @@ void update_zii_ios(void)
 /*----------------------------------------------------------------------------+
   | update_uic_0_3_irq_ios().
   +----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(void)
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
 	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
@@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void)
 /*----------------------------------------------------------------------------+
   | update_uic_4_9_irq_ios().
   +----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(void)
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
@@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void)
 /*----------------------------------------------------------------------------+
   | update_dma_a_b_ios().
   +----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(void)
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
 	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
@@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void)
 /*----------------------------------------------------------------------------+
   | update_dma_c_d_ios().
   +----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(void)
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
 	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
@@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void)
 /*----------------------------------------------------------------------------+
   | update_ebc_master_ios().
   +----------------------------------------------------------------------------*/
-void update_ebc_master_ios(void)
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
 	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
@@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void)
 /*----------------------------------------------------------------------------+
   | update_usb2_device_ios().
   +----------------------------------------------------------------------------*/
-void update_usb2_device_ios(void)
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
 	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
@@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void)
 /*----------------------------------------------------------------------------+
   | update_pci_patch_ios().
   +----------------------------------------------------------------------------*/
-void update_pci_patch_ios(void)
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
 	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
 }
 
 /*----------------------------------------------------------------------------+
-  |   set_chip_gpio_configuration(unsigned char gpio_core)
+  |   set_chip_gpio_configuration(unsigned char gpio_core,
+  |                               gpio_param_s (*gpio_tab)[GPIO_MAX])
   |   Put the core impacted by clock modification and sharing in reset.
   |   Config the select registers to resolve the sharing depending of the config.
   |   Configure the GPIO registers.
   |
   +----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core)
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
 {
 	unsigned char i=0, j=0, reg_offset = 0;
 	unsigned long gpio_reg, gpio_core_add;
@@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void)
 			CORE_NOT_SELECTED	/* PCI_PATCH */
 		};
 
+	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 
 	/* Table Default Initialisation + FPGA Access */
-	init_default_gpio();
+	init_default_gpio(gpio_tab);
-	set_chip_gpio_configuration(GPIO0);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
-	set_chip_gpio_configuration(GPIO1);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
 
 	/* Update Table */
 	force_bup_core_selection(ppc440ep_core_selection, &config_val);
@@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void)
 	/* UIC 0:3 Selection */
 	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
 	{
-		update_uic_0_3_irq_ios();
+		update_uic_0_3_irq_ios(gpio_tab);
 		dma_a_b_unselect_in_fpga();
 	}
 
@@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void)
 	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
-		update_uic_4_9_irq_ios();
+		update_uic_4_9_irq_ios(gpio_tab);
 	}
 
 	/* DMA AB Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
-		update_dma_a_b_ios();
+		update_dma_a_b_ios(gpio_tab);
 		dma_a_b_selection_in_fpga();
 	}
 
 	/* DMA CD Selection */
 	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
 	{
-		update_dma_c_d_ios();
+		update_dma_c_d_ios(gpio_tab);
 		dma_c_d_selection_in_fpga();
 	}
 
@@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_ebc_master_ios();
+		update_ebc_master_ios(gpio_tab);
 	}
 
 	/* PCI Patch Enable */
 	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
 	{
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_pci_patch_ios();
+		update_pci_patch_ios(gpio_tab);
 	}
 
 	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
@@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void)
 	/* USB2.0 Device Selection */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
 	{
-		update_usb2_device_ios();
+		update_usb2_device_ios(gpio_tab);
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
 
@@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void)
 	/* NAND Flash Selection */
 	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
 	{
-		update_ndfc_ios();
+		update_ndfc_ios(gpio_tab);
 
 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 		mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
@@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void)
 	/* MII Selection */
 	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void)
 	/* RMII Selection */
 	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void)
 	/* SMII Selection */
 	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
 	{
-		update_zii_ios();
+		update_zii_ios(gpio_tab);
 		mfsdr(sdr_mfr, sdr0_mfr);
 		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
 		mtsdr(sdr_mfr, sdr0_mfr);
@@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void)
 		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
 		break;
 	}
-	update_uart_ios(uart_configuration);
+	update_uart_ios(uart_configuration, gpio_tab);
 
 	/* UART Selection in all cases */
 	uart_selection_in_fpga(uart_configuration);
@@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void)
 
 	/* Perform effective access to hardware */
 	mtsdr(sdr_pfc1, sdr0_pfc1);
-	set_chip_gpio_configuration(GPIO0);
+	set_chip_gpio_configuration(GPIO0, gpio_tab);
-	set_chip_gpio_configuration(GPIO1);
+	set_chip_gpio_configuration(GPIO1, gpio_tab);
 
 	/* USB2.0 Device Reset must be done after GPIO setting */
 	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)

board/amcc/bamboo/init.S

@@ -51,13 +51,12 @@ tlbtab:
 	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #else
 	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 #endif
 
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
 	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-
 	/* PCI base & peripherals */
 	tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
 

board/amcc/bamboo/u-boot.lds

@@ -141,8 +141,6 @@ SECTIONS
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
-
   _end = . ;
   PROVIDE (end = .);
 }

board/amcc/bubinga/bubinga.c

@@ -20,10 +20,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-long int spd_sdram(void);
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
 
 int board_early_init_f(void)
 {
@@ -34,6 +36,15 @@ int board_early_init_f(void)
 	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter if selected
+	 */
+	if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+		mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+	else
+		mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
+
 	return 0;
 }
 

board/amcc/common/flash.c

@@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 		if (info->flash_id & FLASH_BTYPE) {
 			/* set sector offsets for bottom boot block type */
 			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
+			info->start[1] = base + 0x00002000;
-			info->start[2] = base + 0x00006000;
+			info->start[2] = base + 0x00004000;
-			info->start[3] = base + 0x00008000;
+			info->start[3] = base + 0x00006000;
-			for (i = 4; i < info->sector_count; i++) {
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000a000;
+			info->start[6] = base + 0x0000c000;
+			info->start[7] = base + 0x0000e000;
+			for (i = 8; i < info->sector_count; i++) {
 				info->start[i] =
-				    base + (i * 0x00010000) - 0x00030000;
+				    base + ((i-7) * 0x00010000);
 			}
 		} else {
 			/* set sector offsets for top boot block type */
 			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00002000;
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00006000;
 			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000a000;
+			info->start[i--] = base + info->size - 0x0000c000;
+			info->start[i--] = base + info->size - 0x0000e000;
 			for (; i >= 0; i--) {
 				info->start[i] = base + i * 0x00010000;
 			}

board/amcc/katmai/init.S

@@ -67,9 +67,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -109,9 +109,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

board/amcc/katmai/katmai.c

@@ -34,6 +34,8 @@
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int ppc440spe_init_pcie_rootport(int port);
 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
 
@@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -392,16 +392,18 @@ int katmai_pcie_card_present(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for katmai card presence */
 		if (!katmai_pcie_card_present(i))
@@ -418,8 +420,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
+		hose->last_busno = bus;
-		bus++;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -439,10 +441,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }

board/amcc/luan/luan.c

@@ -104,6 +104,13 @@ int checkboard(void)
 	return  0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
 
 /*************************************************************************
  *  int testdram()

board/amcc/sequoia/cmd_sequoia.c

@@ -26,76 +26,185 @@
 #include <command.h>
 #include <i2c.h>
 
-static u8 boot_533_nor[] = {
+/*
-	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
+ * There are 2 versions of production Sequoia & Rainier platforms.
-	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ * The primary difference is the reference clock. Those with
+ * 33333333 reference clocks will also have 667MHz rated
+ * processors. Not enough differences to have unique clock
+ * settings.
+ *
+ * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
+ * values are independent of the rest of the clock settings.
+ *
+ * All Sequoias & Rainiers select from two possible EEPROMs in Boot
+ * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
+ * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
+ * the only  value affected for a 66MHz PCI and simply needs a +0x10.
+ */
+
+#define NAND_COMPATIBLE	0x01
+#define NOR_COMPATIBLE  0x02
+
+/* check with Stefan on CFG_I2C_EEPROM_ADDR */
+#define I2C_EEPROM_ADDR 0x52
+
+static char *config_labels[] = {
+	"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
+	"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+	NULL
 };
 
-static u8 boot_533_nand[] = {
+static u8 boot_configs[][17] = {
-	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
+	{
-	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		(NOR_COMPATIBLE),
+		0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+	}
 };
 
-static u8 boot_667_nor[] = {
+/*
-	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
+ * Bytes 6,8,9,11 change for NAND boot
-	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ */
-};
+static u8 nand_boot[] = {
-
+	0xd0,  0xa0, 0x68, 0x58
-static u8 boot_667_nand[] = {
-	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
-	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
 };
 
 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	u8 chip;
+	u8 *buf, bNAND;
-	u8 *buf;
+	int x, y, nbytes, selcfg;
-	int cpu_freq;
+	extern char console_buffer[];
 
-	if (argc < 3) {
+	if (argc < 2) {
 		printf("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 
-	cpu_freq = simple_strtol(argv[1], NULL, 10);
+	if ((strcmp(argv[1], "nor") != 0) &&
-	if (!((cpu_freq == 533) || (cpu_freq == 667))) {
+	    (strcmp(argv[1], "nand") != 0)) {
-		printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
-		return 1;
-	}
-
-	/* use 0x52 as I2C EEPROM address for now */
-	chip = 0x52;
-
-	if ((strcmp(argv[2], "nor") != 0) &&
-	    (strcmp(argv[2], "nand") != 0)) {
 		printf("Unsupported boot-device - only nor|nand support\n");
 		return 1;
 	}
 
-	if (strcmp(argv[2], "nand") == 0) {
+	/* set the nand flag based on provided input */
-		switch (cpu_freq) {
+	if ((strcmp(argv[1], "nand") == 0))
-		default:
+		bNAND = 1;
-		case 533:
+	else
-			buf = boot_533_nand;
+		bNAND = 0;
-			break;
+
-		case 667:
+	printf("Available configurations: \n\n");
-			buf = boot_667_nand;
+
-			break;
+	if (bNAND) {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nand compatible */
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
 		}
 	} else {
-		switch (cpu_freq) {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
-		default:
+			/* filter on nor compatible */
-		case 533:
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
-			buf = boot_533_nor;
+				printf(" %d - %s\n", (y+1), config_labels[x]);
-			break;
+				y++;
-		case 667:
+			}
-			buf = boot_667_nor;
-			break;
 		}
 	}
 
-	if (i2c_write(chip, 0, 1, buf, 16) != 0)
+	do {
-		printf("Error writing to EEPROM at address 0x%x\n", chip);
+		nbytes = readline(" Selection [1-x / quit]: ");
+
+		if (nbytes) {
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+			selcfg = simple_strtol(console_buffer, NULL, 10);
+			if ((selcfg < 1) || (selcfg > y))
+				nbytes = 0;
+		}
+	} while (nbytes == 0);
+
+
+	y = (selcfg - 1);
+
+	for (x = 0; boot_configs[x][0] != 0; x++) {
+		if (bNAND) {
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		} else {
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		}
+	}
+
+	buf = &boot_configs[x][1];
+
+	if (bNAND) {
+		buf[6] = nand_boot[0];
+		buf[8] = nand_boot[1];
+		buf[9] = nand_boot[2];
+		buf[11] = nand_boot[3];
+	}
+
+	/* check CPLD register +5 for PCI 66MHz flag */
+	if (in8(CFG_BCSR_BASE + 5) & 0x01)
+		buf[5] += 0x10;
+
+	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
 	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 
 	printf("Done\n");
@@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
-	bootstrap,	3,	0,	do_bootstrap,
+	bootstrap,	2,	0,	do_bootstrap,
 	"bootstrap - program the I2C bootstrap EEPROM\n",
-	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
+	"<nand|nor> - strap to boot from NAND or NOR flash\n"
 	);

board/amcc/sequoia/init.S

@@ -126,6 +126,9 @@ tlbtab:
 	/* TLB-entry for peripherals */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+	/* TLB-entry PCI IO Space - from sr@denx.de */
+	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
 	tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

board/amcc/taihu/Makefile

@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o flash.o lcd.o update.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/amcc/taihu/config.mk

@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000

board/amcc/taihu/lcd.c

@@ -0,0 +1,257 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define LCD_CMD_ADDR	0x50100002
+#define LCD_DATA_ADDR	0x50100003
+#define LCD_BLK_CTRL	CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+	}
+
+	udelay(50);
+	out_8((u8 *) LCD_DATA_ADDR, val);
+	udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+			udelay(50);
+			break;
+		}
+		udelay(50);
+	}
+
+	if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	out_8((u8 *) LCD_CMD_ADDR, 0x80);
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	puts("LCD: ");
+	out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+	udelay(50);
+	out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+	udelay(2000);
+	out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+	udelay(50);
+	lcd_bl_ctrl(0x02);		/* set backlight on */
+	lcd_put_logo();
+	puts("ready\n");
+
+	return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	out_8((u8 *) LCD_CMD_ADDR, 0x01);
+	udelay(2000);
+
+	return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_puts(argv[1]);
+
+	return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_putc((char)argv[1][0]);
+
+	return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+	udelay(50);
+
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				udelay(50);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				out_8((u8 *) LCD_CMD_ADDR, 0x80);
+				addr_flag = 0x80;
+				udelay(50);
+				count = 0x0;
+			} else if (count >= ( cur_addr & 0xf)) {
+				count -= cur_addr & 0xf ;
+				out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+				addr_flag = 0x80;
+				udelay(50);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+				udelay(50);
+			} else if ((count + (cur_addr & 0xf ))>=  0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+				udelay(50);
+			}
+		} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+			count = 0x0;
+			out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+			udelay(50);
+		}
+	}
+	while (count--) {
+		if (dir == 0)
+			out_8((u8 *) LCD_CMD_ADDR, 0x10);
+		else
+			out_8((u8 *) LCD_CMD_ADDR, 0x14);
+		udelay(50);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcd_cls, 1, 1, do_lcd_clear,
+	"lcd_cls - lcd clear display\n",
+	NULL
+	);
+
+U_BOOT_CMD(
+	lcd_puts, 2, 1, do_lcd_puts,
+	"lcd_puts - display string on lcd\n",
+	"<string> - <string> to be displayed\n"
+	);
+
+U_BOOT_CMD(
+	lcd_putc, 2, 1, do_lcd_putc,
+	"lcd_putc - display char on lcd\n",
+	"<char> - <char> to be displayed\n"
+	);
+
+U_BOOT_CMD(
+	lcd_cur, 3, 1, do_lcd_cur,
+	"lcd_cur - shift cursor on lcd\n",
+	"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+	" <count> - 0..31\n"
+	" <dir>   - 0=backward 1=forward\n"
+	);

board/amcc/taihu/taihu.c

@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <asm/gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+	lcd_init();
+
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000000);
+	mtdcr(uicpr, 0xFFFF7F00);	/* set int polarities */
+	mtdcr(uictr, 0x00000000);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	mtebc(pb3ap, CFG_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
+	mtebc(pb3cr, CFG_EBC_PB3CR);
+
+	/*
+	 * Configure CPC0_PCI to enable PerWE as output
+	 * and enable the internal PCI arbiter
+	 */
+	mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*************************************************************************
+ *  long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+	return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+	char stat;
+	int i;
+
+	stat = in_8((u8 *) CPLD_REG0_ADDR);
+	printf("SW2 status: ");
+	for (i=0; i<4; i++) /* 4-position */
+		printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+	printf("\n");
+	return 0;
+}
+
+U_BOOT_CMD (
+	sw2_stat, 1, 1, do_sw_stat,
+	"sw2_stat - show status of switch 2\n",
+	NULL
+	);
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
+{
+	int led_no;
+
+	if (argc != 3) {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	led_no = simple_strtoul(argv[1], NULL, 16);
+	if (led_no != 1 && led_no != 2) {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	if (strcmp(argv[2],"off") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 1);
+		else
+			gpio_write_bit(31, 1);
+	} else if (strcmp(argv[2],"on") == 0x0) {
+		if (led_no == 1)
+			gpio_write_bit(30, 0);
+		else
+			gpio_write_bit(31, 0);
+	} else {
+		printf("%s", cmd_tp->usage);
+		return -1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	led_ctl, 3, 1, do_led_ctl,
+	"led_ctl	- make led 1 or 2  on or off\n",
+	"<led_no> <on/off>	-  make led <led_no> on/off,\n"
+	"\tled_no is 1 or 2\t"
+	);
+
+#define SPI_CS_GPIO0	0
+#define SPI_SCLK_GPIO14	14
+#define SPI_DIN_GPIO15	15
+#define SPI_DOUT_GPIO16	16
+
+void spi_scl(int bit)
+{
+	gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+	gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+	return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
+}
+
+void taihu_spi_chipsel(int cs)
+{
+	gpio_write_bit(SPI_CS_GPIO0, cs);
+}
+
+spi_chipsel_type spi_chipsel[]= {
+	taihu_spi_chipsel
+};
+
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+	29, 30, 27, 28, 29, 30, 25, 27,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28,
+	29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+	hose->fixup_irq = taihu_pci_fixup_irq;
+	return 1;
+}
+#endif /* CONFIG_PCI */
+
+#ifdef CFG_DRAM_TEST
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+	unsigned long msr;
+	unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
+
+	msr = mfmsr();
+	mtmsr(msr & ~(MSR_EE));
+
+	for (k = 0; k < total_kbytes ;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0)
+			printf("%3d MB\r", k / 1024);
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	mtmsr(msr);
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST */

board/amcc/taihu/u-boot.lds

@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/amcc/taihu/update.c

@@ -0,0 +1,132 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static uchar buf_66[] =
+{
+	0xb5,	/* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+	0x80,	/* 0x01~0x03:ptm1ms =0x80000001 */
+	0x00,
+	0x00,
+	0x00,	/* 0x04~0x06:ptm1la = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x07~0x09:ptm2ma = 0x00000000 */
+	0x00,
+	0x00,
+	0x00,	/* 0x0a~0x0c:ptm2la = 0x00000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x0d~0x0e:vendor id 0x1014*/
+	0x14,
+	0x00,	/* 0x0f~0x10:device id 0x0000*/
+	0x00,
+	0x00,	/* 0x11:revision 0x00 */
+	0x00,	/* 0x12~0x14:class 0x000000 */
+	0x00,
+	0x00,
+	0x10,	/* 0x15~0x16:subsystem vendor id */
+	0xe8,
+	0x00,	/* 0x17~0x18:subsystem device id */
+	0x00,
+	0x61,	/* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+	0x68,	/* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+	0x2d,	/* 0x1b: fwdvb=0b101,fwdva=0b101 */
+	0x82,	/* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+	0xbe,	/* 0x1d: tun[24-31]=0xbe */
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
+{
+	ulong len = 0x20;
+	uchar chip = CFG_I2C_EEPROM_ADDR;
+	uchar *pbuf;
+	uchar base;
+	int i;
+
+	if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+		pbuf = buf_33;
+		base = 0x00;
+	} else {
+		pbuf = buf_66;
+		base = 0x40;
+	}
+
+	for (i = 0; i< len; i++, base++) {
+		if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+			printf("i2c_write fail\n");
+			return 1;
+		}
+		udelay(11000);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD (
+	update_boot_eeprom, 1, 1, update_boot_eeprom,
+	"update_boot_eeprom  - update boot eeprom content\n",
+	NULL
+	);

board/amcc/taishan/taishan.c

@@ -32,6 +32,8 @@
 void show_reset_reg(void);
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int lcd_init(void);
 
 int board_early_init_f (void)
@@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/

board/amcc/yucca/init.S

@@ -70,9 +70,9 @@ tlbtabA:
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
@@ -112,9 +112,9 @@ tlbtabB:
 	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)

board/amcc/yucca/yucca.c

@@ -34,6 +34,8 @@
 #include "yucca.h"
 #include "../cpu/ppc4xx/440spe_pcie.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef PCIE_ENDPOINT
 /* #define PCIE_ENDPOINT 1 */
 
@@ -562,6 +564,40 @@ int checkboard (void)
 	return 0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+	if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+		return 1;
+	else
+		return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_WRDTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+	return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_CLKTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+	return default_val;
+}
+
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {
@@ -634,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-	DECLARE_GLOBAL_DATA_PTR;
-
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
@@ -812,16 +846,18 @@ void yucca_setup_pcie_fpga_endpoint(int port)
 
 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 
-void pcie_setup_hoses(void)
+void pcie_setup_hoses(int busno)
 {
 	struct pci_controller *hose;
 	int i, bus;
+	char *env;
+	unsigned int delay;
 
 	/*
 	 * assume we're called after the PCIX hose is initialized, which takes
 	 * bus ID 0 and therefore start numbering PCIe's from 1.
 	 */
-	bus = 1;
+	bus = busno;
 	for (i = 0; i <= 2; i++) {
 		/* Check for yucca card presence */
 		if (!yucca_pcie_card_present(i))
@@ -840,8 +876,8 @@ void pcie_setup_hoses(void)
 
 		hose = &pcie_hose[i];
 		hose->first_busno = bus;
-		hose->last_busno  = bus;
+		hose->last_busno = bus;
-		bus++;
+		hose->current_busno = bus;
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
@@ -861,10 +897,21 @@ void pcie_setup_hoses(void)
 		 */
 #else
 		ppc440spe_setup_pcie_rootpoint(hose, i);
+
+		env = getenv ("pciscandelay");
+		if (env != NULL) {
+			delay = simple_strtoul (env, NULL, 10);
+			if (delay > 5)
+				printf ("Warning, expect noticable delay before PCIe"
+					"scan due to 'pciscandelay' value!\n");
+			mdelay (delay * 1000);
+		}
+
 		/*
 		 * Config access can only go down stream
 		 */
 		hose->last_busno = pci_hose_scan(hose);
+		bus = hose->last_busno + 1;
 #endif
 	}
 }

board/at91rm9200dk/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= at91rm9200dk.o at45.o flash.o
+COBJS	:= at91rm9200dk.o flash.o led.o mux.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/at91rm9200dk/at45.c

@@ -1,621 +0,0 @@
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
-the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS	(0xC << 16)
-#define DATAFLASH_TCHS	(0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY			200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
-
-void AT91F_SpiInit(void) {
-
-/*-------------------------------------------------------------------*/
-/*	SPI DataFlash Init								*/
-/*-------------------------------------------------------------------*/
-	/* Configure PIOs */
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
-	/* Enable CLock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-	/* Reset the SPI */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-	/* Configure SPI in Master Mode with No CS selected !!! */
-	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
-	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
-	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-}
-
-void AT91F_SpiEnable(int cs) {
-	switch(cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
-		break;
-	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
-		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
-		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
-		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
-		/* Clear Output */
-		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-		/* Configure PCS */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-		break;
-	}
-
-	/* SPI_Enable */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite						      */
-/* \brief Set the PDC registers for a transfert				      */
-/*----------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
-	unsigned int timeout;
-
-	pDesc->state = BUSY;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-	/* Initialize the Transmit and Receive Pointer */
-	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-	/* Intialize the Transmit and Receive Counters */
-	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-	if ( pDesc->tx_data_size != 0 ) {
-		/* Initialize the Next Transmit and Next Receive Pointer */
-		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-		/* Intialize the Next Transmit and Next Receive Counters */
-		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-	}
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
-	timeout = 0;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-	pDesc->state = IDLE;
-
-	if (timeout >= CFG_SPI_WRITE_TOUT){
-		printf("Error Timeout\n\r");
-		return DATAFLASH_ERROR;
-	}
-
-	return DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashSendCommand					*/
-/* \brief Generic function to send a command to the dataflash		*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char OpCode,
-	unsigned int CmdSize,
-	unsigned int DataflashAddress)
-{
-    unsigned int adr;
-
-	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* process the address to obtain page address and byte address */
-	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
-	/* fill the  command  buffer */
-	pDataFlash->pDataFlashDesc->command[0] = OpCode;
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
-	} else {
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
-		pDataFlash->pDataFlashDesc->command[4] = 0;
-	}
-	pDataFlash->pDataFlashDesc->command[5] = 0;
-	pDataFlash->pDataFlashDesc->command[6] = 0;
-	pDataFlash->pDataFlashDesc->command[7] = 0;
-
-	/* Initialize the SpiData structure for the spi write fuction */
-	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
-
-	/* send the command and read the data */
-	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashGetStatus					*/
-/* \brief Read the status register of the dataflash			*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
-	AT91S_DataFlashStatus status;
-
-	/* if a transfert is in progress ==> return 0 */
-	if( (pDesc->state) != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* first send the read status command (D7H) */
-	pDesc->command[0] = DB_STATUS;
-	pDesc->command[1] = 0;
-
-	pDesc->DataFlash_state  = GET_STATUS;
-	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
-	pDesc->tx_cmd_pt 		= pDesc->command ;
-	pDesc->rx_cmd_pt 		= pDesc->command ;
-	pDesc->rx_cmd_size 		= 2 ;
-	pDesc->tx_cmd_size 		= 2 ;
-	status = AT91F_SpiWrite (pDesc);
-
-	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-
-	return status;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashWaitReady					*/
-/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
-{
-	pDataFlashDesc->DataFlash_state = IDLE;
-
-	do {
-		AT91F_DataFlashGetStatus(pDataFlashDesc);
-		timeout--;
-	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
-
-	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
-		return DATAFLASH_ERROR;
-
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashContinuousRead 				*/
-/* Object              : Continuous stream Read 				*/
-/* Input Parameters    : DataFlash Service					*/
-/*						: <src> = dataflash address	*/
-/*                     : <*dataBuffer> = data buffer pointer			*/
-/*                     : <sizeToRead> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
-	AT91PS_DataFlash pDataFlash,
-	int src,
-	unsigned char *dataBuffer,
-	int sizeToRead )
-{
-	AT91S_DataFlashStatus status;
-	/* Test the size to read in the device */
-	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return DATAFLASH_MEMORY_OVERFLOW;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
-	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-
-	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
-	/* Send the command to the dataflash */
-	return(status);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
-/* Object              : Main memory page program through buffer 1 or buffer 2	*/
-/* Input Parameters    : DataFlash Service					*/
-/*						: <*src> = Source buffer	*/
-/*                     : <dest> = dataflash destination address			*/
-/*                     : <SizeToWrite> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int SizeToWrite)
-{
-	int cmdsize;
-	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
-	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-	pDataFlash->pDataFlashDesc->rx_data_pt = src;
-	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
-
-	cmdsize = 4;
-	/* Send the command to the dataflash */
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
-/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
-		return DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name       : AT91F_DataFlashWriteBuffer				*/
-/* Object              : Write data to the internal sram buffer 1 or 2		*/
-/* Input Parameters    : DataFlash Service					*/
-/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
-/*                     : <*dataBuffer> = data buffer to write			*/
-/*                     : <bufferAddress> = address in the internal buffer	*/
-/*                     : <SizeToWrite> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned char *dataBuffer,
-	unsigned int bufferAddress,
-	int SizeToWrite )
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
-		return DATAFLASH_BAD_COMMAND;
-
-	/* buffer address must be lower than page size */
-	if (bufferAddress > pDataFlash->pDevice->pages_size)
-		return DATAFLASH_BAD_ADDRESS;
-
-	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* Send first Write Command */
-	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
-	pDataFlash->pDataFlashDesc->command[1] = 0;
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-	    	pDataFlash->pDataFlashDesc->command[2] = 0;
-	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-		cmdsize = 5;
-	} else {
-	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-	    	pDataFlash->pDataFlashDesc->command[4] = 0;
-		cmdsize = 4;
-	}
-
-	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
-	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
-	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
-	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
-
-	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PageErase                                        */
-/* Object              : Erase a page 						*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PageErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_BlockErase                                       */
-/* Object              : Erase a Block 						*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_BlockErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int block)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_WriteBufferToMain				*/
-/* Object              : Write buffer to the main memory			*/
-/* Input Parameters    : DataFlash Service					*/
-/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
-/*                     : <dest> = main memory address				*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int dest )
-{
-	int cmdsize;
-	/* Test if the buffer command is correct */
-	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
-		return DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	/* Send the command to the dataflash */
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PartialPageWrite					*/
-/* Object              : Erase partielly a page					*/
-/* Input Parameters    : <page> = page number					*/
-/*			: <AdrInpage> = adr to begin the fading			*/
-/*                     : <length> = Number of bytes to erase			*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int size)
-{
-	unsigned int page;
-	unsigned int AdrInPage;
-
-	page = dest / (pDataFlash->pDevice->pages_size);
-	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
-	/* Read the contents of the page in the Sram Buffer */
-	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	/*Update the SRAM buffer */
-	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-	/* Erase page if a 128 Mbits device */
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-		AT91F_PageErase(pDataFlash, page);
-		/* Rewrite the modified Sram Buffer in the main memory */
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	}
-
-	/* Rewrite the modified Sram Buffer in the main memory */
-	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashWrite					*/
-/* Object              :							*/
-/* Input Parameters    : <*src> = Source buffer					*/
-/*                     : <dest> = dataflash adress				*/
-/*                     : <size> = data buffer size				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	int dest,
-	int size )
-{
-	unsigned int length;
-	unsigned int page;
-	unsigned int status;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return DATAFLASH_MEMORY_OVERFLOW;
-
-	/* If destination does not fit a page start address */
-	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
-		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
-		if (size < length)
-			length = size;
-
-		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		/* Update size, source and destination pointers */
-		size -= length;
-		dest += length;
-		src += length;
-	}
-
-	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
-		/* program dataflash page */
-		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
-		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		status = AT91F_PageErase(pDataFlash, page);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-		if (!status)
-			return DATAFLASH_ERROR;
-
-		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
-		if(!status)
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		/* Update size, source and destination pointers */
-		size -= pDataFlash->pDevice->pages_size ;
-		dest += pDataFlash->pDevice->pages_size ;
-		src  += pDataFlash->pDevice->pages_size ;
-	}
-
-	/* If still some bytes to read */
-	if ( size > 0 ) {
-		/* program dataflash page */
-		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	}
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashRead 					*/
-/* Object              : Read a block in dataflash				*/
-/* Input Parameters    : 							*/
-/* Return value		: 							*/
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
-	AT91PS_DataFlash pDataFlash,
-	unsigned long addr,
-	unsigned long size,
-	char *buffer)
-{
-	unsigned long SizeToRead;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
-		return -1;
-
-	while (size) {
-		SizeToRead = (size < 0x8000)? size:0x8000;
-
-		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
-			return -1;
-
-		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
-			return -1;
-
-		size -= SizeToRead;
-		addr += SizeToRead;
-		buffer += SizeToRead;
-	}
-
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataflashProbe 					*/
-/* Object              : 							*/
-/* Input Parameters    : 							*/
-/* Return value	       : Dataflash status register				*/
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
-	AT91F_SpiEnable(cs);
-	AT91F_DataFlashGetStatus(pDesc);
-	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
-}
-
-#endif

board/at91rm9200dk/led.c

@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+
+#define	GREEN_LED	AT91C_PIO_PB0
+#define	YELLOW_LED	AT91C_PIO_PB1
+#define	RED_LED	AT91C_PIO_PB2
+
+void	green_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= GREEN_LED;
+}
+
+void	 yellow_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= YELLOW_LED;
+}
+
+void	 red_LED_on(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_CODR		= RED_LED;
+}
+
+void	green_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= GREEN_LED;
+}
+
+void	yellow_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= YELLOW_LED;
+}
+
+void	red_LED_off(void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	PIOB->PIO_SODR		= RED_LED;
+}
+
+
+void LED_init (void)
+{
+	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+	AT91PS_PMC	PMC	= AT91C_BASE_PMC;
+	PMC->PMC_PCER		= (1 << AT91C_ID_PIOB);	/* Enable PIOB clock */
+	/* Disable peripherals on LEDs */
+	PIOB->PIO_PER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+	/* Enable pins as outputs */
+	PIOB->PIO_OER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+	/* Turn all LEDs OFF */
+	PIOB->PIO_SODR		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+}

board/at91rm9200dk/mux.c

@@ -0,0 +1,37 @@
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+int AT91F_GetMuxStatus(void) {
+#ifdef	DATAFLASH_MMC_SELECT
+	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
+
+
+	if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) {
+		return 1;
+	} else {
+		return 0;
+	}
+#endif
+	return 0;
+}
+
+void AT91F_SelectMMC(void) {
+#ifdef	DATAFLASH_MMC_SELECT
+	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT;	/* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT;	/* Configure in output */
+	/* Set Output */
+	AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT;
+#endif
+}
+
+void AT91F_SelectSPI(void) {
+#ifdef	DATAFLASH_MMC_SELECT
+	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT;	/* Set in PIO mode */
+	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT;	/* Configure in output */
+	/* Clear Output */
+	AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT;
+#endif
+}

board/bf533-ezkit/bf533-ezkit.c

@@ -30,6 +30,8 @@
 #include "psd4256.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 #if (BFIN_CPU == ADSP_BF531)
@@ -46,7 +48,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/bf533-stamp/bf533-stamp.c

@@ -30,6 +30,8 @@
 #include <asm/io.h>
 #include "bf533-stamp.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define STATUS_LED_OFF 0
 #define STATUS_LED_ON  1
 
@@ -55,7 +57,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	printf("SDRAM attributes:\n");
 	printf

board/bf537-stamp/bf537-stamp.c

@@ -32,6 +32,8 @@
 #include <asm/io.h>
 #include "ether_bf537.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define POST_WORD_ADDR 0xFF903FFC
 
 /*
@@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/bf561-ezkit/bf561-ezkit.c

@@ -29,6 +29,8 @@
 #include <common.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	printf("CPU:   ADSP BF561\n");
@@ -39,7 +41,6 @@ int checkboard(void)
 
 long int initdram(int board_type)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");

board/cds/common/via.c

@@ -28,11 +28,16 @@ void mpc85xx_config_via(struct pci_controller *hose,
 			pci_dev_t dev, struct pci_config_table *tab)
 {
 	pci_dev_t bridge;
+	unsigned int cmdstat;
 
 	/* Enable USB and IDE functions */
 	pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
 
-	pciauto_config_device(hose, dev);
+	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+	cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 
 	/*
 	 * Force the backplane P2P bridge to have a window
@@ -40,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose,
 	 * This allows legacy I/O (i8259, etc) on the VIA
 	 * southbridge to be accessed.
 	 */
-	bridge = PCI_BDF(0,17,0);
+	bridge = PCI_BDF(0,BRIDGE_ID,0);
 	pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
 	pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
 	pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);

board/cds/mpc8541cds/mpc8541cds.c

@@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
 	{},
 };
 

board/cds/mpc8548cds/config.mk

@@ -1,5 +1,5 @@
 #
-# Copyright 2004 Freescale Semiconductor.
+# Copyright 2004, 2007 Freescale Semiconductor.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -23,7 +23,9 @@
 #
 # mpc8548cds board
 #
+ifndef TEXT_BASE
 TEXT_BASE = 0xfff80000
+endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_E500=1
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1

board/cds/mpc8548cds/init.S

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  * Copyright 2002,2003, Motorola Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,12 @@
 #include <config.h>
 #include <mpc85xx.h>
 
+#define LAWAR_TRGT_PCI1		0x00000000
+#define LAWAR_TRGT_PCI2		0x00100000
+#define LAWAR_TRGT_PCIE		0x00200000
+#define LAWAR_TRGT_RIO		0x00c00000
+#define LAWAR_TRGT_LBC		0x00400000
+#define LAWAR_TRGT_DDR		0x00f00000
 
 /*
  * TLB0 and TLB1 Entries
@@ -47,8 +53,8 @@
  */
 
 #define	entry_start \
-	mflr	r1 	;	\
+	mflr	r1	;	\
-	bl	0f 	;
+	bl	0f	;
 
 #define	entry_end \
 0:	mflr	r0	;	\
@@ -84,8 +90,8 @@ tlb1_entry:
 #endif
 
 	/*
-	 * TLB0		16K	Cacheable, non-guarded
+	 * TLB0		16K	Cacheable, guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 * Temporary Global data for initialization
 	 *
 	 * Use four 4K TLB0 entries.  These entries must be cacheable
 	 * as they provide the bootstrap memory before the memory
@@ -97,28 +103,28 @@ tlb1_entry:
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
@@ -130,51 +136,44 @@ tlb1_entry:
 	 */
 	.long TLB1_MAS0(1, 0, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
+	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM
+	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
 	 */
 	.long TLB1_MAS0(1, 1, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
 
+#ifdef CFG_RIO_MEM_PHYS
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI2 MEM
 	 */
 	.long TLB1_MAS0(1, 2, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
 			0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS),	0,0,0,0,0,1,0,1,0,1)
-			0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 3:	1GB	Non-cacheable, guarded
+	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xa0000000	256M	PEX MEM First half
-	 * 0xb0000000	256M	PEX MEM Second half
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
 	.long TLB1_MAS0(1, 3, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+			0,0,0,0,1,0,1,0)
-
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
-	/*
+			0,0,0,0,0,1,0,1,0,1)
-	 * TLB 4:	Reserved for future usage
+#endif
-	 */
-
 	/*
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	8M	PCI1 IO
+	 * 0xe200_0000	1M	PCI1 IO
-	 * 0xe280_0000	8M	PCI2 IO
+	 * 0xe210_0000	1M	PCI2 IO
-	 * 0xe300_0000	16M	PEX IO
+	 * 0xe300_0000	1M	PCIe IO
 	 */
 	.long TLB1_MAS0(1, 5, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
@@ -187,17 +186,18 @@ tlb1_entry:
 	 */
 	.long TLB1_MAS0(1, 6, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
+	 * TLB 7:	64M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
+	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
 	 */
 	.long TLB1_MAS0(1, 7, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
 2:
 	entry_end
 
@@ -205,14 +205,13 @@ tlb1_entry:
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x8fff_ffff     PCI1 MEM                256M
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0x9000_0000     0x9fff_ffff     PCI2 MEM                256M
+ * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
- * 0xa000_0000     0xbfff_ffff     PEX MEM                 512M
  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
  * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe27f_ffff     PCI1 IO                 8M
+ * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
- * 0xe280_0000     0xe2ff_ffff     PCI2 IO                 8M
+ * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
- * 0xe300_0000     0xe3ff_ffff     PEX IO                  16M
+ * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
@@ -222,47 +221,50 @@ tlb1_entry:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  *
- * The defines below are 1-off of the actual LAWAR0 usage.
+ * LAW 0 is reserved for boot mapping
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
  */
 
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
-
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
-
-#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR6 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
-#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR7 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
-
-#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR8  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
-
 	.section .bootpg, "ax"
 	.globl	law_entry
-
 law_entry:
 	entry_start
+
 	.long (4f-3f)/8
 3:
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long  0
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
+	.long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-	.long LAWBAR8,LAWAR8
+
+#ifdef CFG_PCI1_MEM_PHYS
+	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCI2_MEM_PHYS
+	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCIE1_MEM_PHYS
+	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+#ifdef CFG_RIO_MEM_PHYS
+	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
 4:
 	entry_end

board/cds/mpc8548cds/mpc8548cds.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -26,6 +26,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <miiphy.h>
 
@@ -33,10 +34,15 @@
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern long int spd_sdram(void);
 
 void local_bus_init(void);
@@ -56,13 +62,6 @@ int checkboard (void)
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
 
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
-	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-
-	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
-
 	uint cpu_board_rev = get_cpu_board_revision ();
 
 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
@@ -71,20 +70,6 @@ int checkboard (void)
 	printf ("CPU Board Revision %d.%d (0x%04x)\n",
 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
-	printf ("    PCI1: %d bit, %s MHz, %s\n",
-		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
-		pci1_clk_sel ? "sync" : "async");
-
-	if (pci_dual) {
-		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf ("    PCI2: disabled\n");
-	}
-
 	/*
 	 * Initialize local bus.
 	 */
@@ -102,6 +87,8 @@ int checkboard (void)
 	 */
 	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
 
+	ecm->eedr = 0xffffffff;		/* clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* enable ecm errors */
 	return 0;
 }
 
@@ -176,6 +163,9 @@ local_bus_init(void)
 	lbc->lcrr |= 0x00030000;
 
 	asm("sync;isync;msync");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
 }
 
 /*
@@ -301,7 +291,7 @@ testdram(void)
 }
 #endif
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 /* For some reason the Tundra PCI bridge shows up on itself as a
  * different device.  Work around that by refusing to configure it.
  */
@@ -309,32 +299,197 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
 	{},
 };
 
-static struct pci_controller hose[] = {
+static struct pci_controller pci1_hose = {
-	{ config_table: pci_mpc85xxcds_config_table,},
+	config_table: pci_mpc85xxcds_config_table};
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
-#endif
-};
-
 #endif	/* CONFIG_PCI */
 
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif	/* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif	/* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
 void
 pci_init_board(void)
 {
-#ifdef CONFIG_PCI
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	pci_mpc85xx_init(&hose);
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+	struct pci_config_table *table;
+
+	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
+	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
+	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
+
+	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter"
+			);
+
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCI_MEMORY_BUS,
+			       CFG_PCI_MEMORY_PHYS,
+			       CFG_PCI_MEMORY_SIZE,
+			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			       CFG_PCI1_MEM_BASE,
+			       CFG_PCI1_MEM_PHYS,
+			       CFG_PCI1_MEM_SIZE,
+			       PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			       CFG_PCI1_IO_BASE,
+			       CFG_PCI1_IO_PHYS,
+			       CFG_PCI1_IO_SIZE,
+			       PCI_REGION_IO);
+		hose->region_count = 3;
+
+		/* relocate config table pointers */
+		hose->config_table = \
+			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+		for (table = hose->config_table; table && table->vendor; table++)
+			table->config_device += gd->reloc_off;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		first_free_busno=hose->last_busno+1;
+		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+			/* PCI-X init */
+			if (CONFIG_SYS_CLK_FREQ < 66000000)
+				printf("PCI-X will only work at 66 MHz\n");
+
+			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+		}
 #endif
+	} else {
+		printf ("    PCI: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie1_hose;
+	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+	int pcie_configured  = io_sel >= 1;
+
+	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n    PCIE connected to slot as %s (base address %x)",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
+		}
+		printf ("\n");
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCI_MEMORY_BUS,
+			       CFG_PCI_MEMORY_PHYS,
+			       CFG_PCI_MEMORY_SIZE,
+			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			       CFG_PCIE1_MEM_BASE,
+			       CFG_PCIE1_MEM_PHYS,
+			       CFG_PCIE1_MEM_SIZE,
+			       PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			       CFG_PCIE1_IO_BASE,
+			       CFG_PCIE1_IO_PHYS,
+			       CFG_PCIE1_IO_SIZE,
+			       PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+		first_free_busno=hose->last_busno+1;
+
+	} else {
+		printf ("    PCIE: disabled\n");
+	}
+ }
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
 }
 
 int last_stage_init(void)
@@ -367,3 +522,32 @@ int last_stage_init(void)
 
 	return 0;
 }
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+
+#ifdef CONFIG_PCI1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+
+#ifdef CONFIG_PCIE1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+}
+#endif

board/cds/mpc8548cds/u-boot.lds

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -71,7 +71,6 @@ SECTIONS
     cpu/mpc85xx/cpu.o (.text)
     drivers/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)

board/cds/mpc8555cds/mpc8555cds.c

@@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
 
 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
 		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+		mpc85xx_config_via_usb2, {0,0,0}},
+	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
 		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+		mpc85xx_config_via_ac97, {0,0,0}},
 	{},
 };
 

board/cm5200/cm5200.c

@@ -122,7 +122,7 @@ long int initdram(int board_type)
 	mem_conf_t *mem_conf;
 
 	mem_conf = get_mem_config(board_type);
-	
+
 	/* configure SDRAM start/end for detection */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
 
@@ -303,7 +303,7 @@ int checkboard(void)
 	hw_id_t hw_id_tmp;
 	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
 
-	/* 
+	/*
 	 * We need I2C to access HW ID data from EEPROM, so we call i2c_init()
 	 * here despite the fact that it will be called again later on. We
 	 * also use a little trick to silence I2C-related output.
@@ -321,7 +321,7 @@ int checkboard(void)
 	else
 		printf("Board: unrecognized cm5200 module (%s)\n",
 			module_name_tmp);
-	
+
 	return 0;
 }
 

board/cm5200/cm5200.h

@@ -138,7 +138,7 @@ static char **hw_id_list[] = {
 	cmu1_qa_hw_id,
 };
 
-/* indices to the above list - keep in sync */ 
+/* indices to the above list - keep in sync */
 enum {
 	CM1_QA,
 	CM11_QA,

board/cm5200/cmd_cm5200.c

@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
  *
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com> 
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,7 +27,7 @@
 #include <i2c.h>
 #include <usb.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#ifdef CONFIG_CMD_BSP
 
 int do_i2c(char *argv[])
 {
@@ -445,4 +445,4 @@ U_BOOT_CMD(
 	"fkt usb\n"
 	"     - Test USB communication\n"
 );
-#endif /* CFG_CMD_BSP */
+#endif /* CONFIG_CMD_BSP */

board/cmc_pu2/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
+COBJS	:= cmc_pu2.o flash.o load_sernum_ethaddr.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/cmc_pu2/at45.c

@@ -1,621 +0,0 @@
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
-the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS	(0xC << 16)
-#define DATAFLASH_TCHS	(0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY			200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
-
-void AT91F_SpiInit(void) {
-
-/*-------------------------------------------------------------------*/
-/*	SPI DataFlash Init								*/
-/*-------------------------------------------------------------------*/
-	/* Configure PIOs */
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
-	/* Enable CLock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-	/* Reset the SPI */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-	/* Configure SPI in Master Mode with No CS selected !!! */
-	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
-	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
-	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-}
-
-void AT91F_SpiEnable(int cs) {
-	switch(cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
-		break;
-	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
-		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
-		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
-		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
-		/* Clear Output */
-		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-		/* Configure PCS */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-		break;
-	}
-
-	/* SPI_Enable */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite						      */
-/* \brief Set the PDC registers for a transfert				      */
-/*----------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
-	unsigned int timeout;
-
-	pDesc->state = BUSY;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-	/* Initialize the Transmit and Receive Pointer */
-	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-	/* Intialize the Transmit and Receive Counters */
-	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-	if ( pDesc->tx_data_size != 0 ) {
-		/* Initialize the Next Transmit and Next Receive Pointer */
-		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-		/* Intialize the Next Transmit and Next Receive Counters */
-		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-	}
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
-	timeout = 0;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-	pDesc->state = IDLE;
-
-	if (timeout >= CFG_SPI_WRITE_TOUT){
-		printf("Error Timeout\n\r");
-		return DATAFLASH_ERROR;
-	}
-
-	return DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashSendCommand					*/
-/* \brief Generic function to send a command to the dataflash		*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char OpCode,
-	unsigned int CmdSize,
-	unsigned int DataflashAddress)
-{
-    unsigned int adr;
-
-	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* process the address to obtain page address and byte address */
-	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
-	/* fill the  command  buffer */
-	pDataFlash->pDataFlashDesc->command[0] = OpCode;
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
-	} else {
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
-		pDataFlash->pDataFlashDesc->command[4] = 0;
-	}
-	pDataFlash->pDataFlashDesc->command[5] = 0;
-	pDataFlash->pDataFlashDesc->command[6] = 0;
-	pDataFlash->pDataFlashDesc->command[7] = 0;
-
-	/* Initialize the SpiData structure for the spi write fuction */
-	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
-
-	/* send the command and read the data */
-	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashGetStatus					*/
-/* \brief Read the status register of the dataflash			*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
-	AT91S_DataFlashStatus status;
-
-	/* if a transfert is in progress ==> return 0 */
-	if( (pDesc->state) != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* first send the read status command (D7H) */
-	pDesc->command[0] = DB_STATUS;
-	pDesc->command[1] = 0;
-
-	pDesc->DataFlash_state  = GET_STATUS;
-	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
-	pDesc->tx_cmd_pt 		= pDesc->command ;
-	pDesc->rx_cmd_pt 		= pDesc->command ;
-	pDesc->rx_cmd_size 		= 2 ;
-	pDesc->tx_cmd_size 		= 2 ;
-	status = AT91F_SpiWrite (pDesc);
-
-	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-
-	return status;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashWaitReady					*/
-/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
-/*----------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
-{
-	pDataFlashDesc->DataFlash_state = IDLE;
-
-	do {
-		AT91F_DataFlashGetStatus(pDataFlashDesc);
-		timeout--;
-	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
-
-	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
-		return DATAFLASH_ERROR;
-
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashContinuousRead 				*/
-/* Object              : Continuous stream Read 				*/
-/* Input Parameters    : DataFlash Service					*/
-/*						: <src> = dataflash address	*/
-/*                     : <*dataBuffer> = data buffer pointer			*/
-/*                     : <sizeToRead> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
-	AT91PS_DataFlash pDataFlash,
-	int src,
-	unsigned char *dataBuffer,
-	int sizeToRead )
-{
-	AT91S_DataFlashStatus status;
-	/* Test the size to read in the device */
-	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return DATAFLASH_MEMORY_OVERFLOW;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
-	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-
-	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
-	/* Send the command to the dataflash */
-	return(status);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
-/* Object              : Main memory page program through buffer 1 or buffer 2	*/
-/* Input Parameters    : DataFlash Service					*/
-/*						: <*src> = Source buffer	*/
-/*                     : <dest> = dataflash destination address			*/
-/*                     : <SizeToWrite> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int SizeToWrite)
-{
-	int cmdsize;
-	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
-	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-	pDataFlash->pDataFlashDesc->rx_data_pt = src;
-	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
-
-	cmdsize = 4;
-	/* Send the command to the dataflash */
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
-/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
-		return DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name       : AT91F_DataFlashWriteBuffer				*/
-/* Object              : Write data to the internal sram buffer 1 or 2		*/
-/* Input Parameters    : DataFlash Service					*/
-/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
-/*                     : <*dataBuffer> = data buffer to write			*/
-/*                     : <bufferAddress> = address in the internal buffer	*/
-/*                     : <SizeToWrite> = data buffer size			*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned char *dataBuffer,
-	unsigned int bufferAddress,
-	int SizeToWrite )
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
-		return DATAFLASH_BAD_COMMAND;
-
-	/* buffer address must be lower than page size */
-	if (bufferAddress > pDataFlash->pDevice->pages_size)
-		return DATAFLASH_BAD_ADDRESS;
-
-	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
-		return DATAFLASH_BUSY;
-
-	/* Send first Write Command */
-	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
-	pDataFlash->pDataFlashDesc->command[1] = 0;
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-	    	pDataFlash->pDataFlashDesc->command[2] = 0;
-	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-		cmdsize = 5;
-	} else {
-	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-	    	pDataFlash->pDataFlashDesc->command[4] = 0;
-		cmdsize = 4;
-	}
-
-	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
-	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
-	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
-	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
-
-	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PageErase                                        */
-/* Object              : Erase a page 						*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PageErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_BlockErase                                       */
-/* Object              : Erase a Block 						*/
-/* Input Parameters    : DataFlash Service					*/
-/*                     : Page concerned						*/
-/*                     : 							*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_BlockErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int block)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_WriteBufferToMain				*/
-/* Object              : Write buffer to the main memory			*/
-/* Input Parameters    : DataFlash Service					*/
-/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
-/*                     : <dest> = main memory address				*/
-/* Return value		: State of the dataflash				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_WriteBufferToMain (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int dest )
-{
-	int cmdsize;
-	/* Test if the buffer command is correct */
-	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
-		return DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	/* Send the command to the dataflash */
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PartialPageWrite					*/
-/* Object              : Erase partielly a page					*/
-/* Input Parameters    : <page> = page number					*/
-/*			: <AdrInpage> = adr to begin the fading			*/
-/*                     : <length> = Number of bytes to erase			*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_PartialPageWrite (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int size)
-{
-	unsigned int page;
-	unsigned int AdrInPage;
-
-	page = dest / (pDataFlash->pDevice->pages_size);
-	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
-	/* Read the contents of the page in the Sram Buffer */
-	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	/*Update the SRAM buffer */
-	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-	/* Erase page if a 128 Mbits device */
-	if (pDataFlash->pDevice->pages_number >= 16384) {
-		AT91F_PageErase(pDataFlash, page);
-		/* Rewrite the modified Sram Buffer in the main memory */
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	}
-
-	/* Rewrite the modified Sram Buffer in the main memory */
-	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashWrite					*/
-/* Object              :							*/
-/* Input Parameters    : <*src> = Source buffer					*/
-/*                     : <dest> = dataflash adress				*/
-/*                     : <size> = data buffer size				*/
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	int dest,
-	int size )
-{
-	unsigned int length;
-	unsigned int page;
-	unsigned int status;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return DATAFLASH_MEMORY_OVERFLOW;
-
-	/* If destination does not fit a page start address */
-	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
-		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
-		if (size < length)
-			length = size;
-
-		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		/* Update size, source and destination pointers */
-		size -= length;
-		dest += length;
-		src += length;
-	}
-
-	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
-		/* program dataflash page */
-		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
-		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		status = AT91F_PageErase(pDataFlash, page);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-		if (!status)
-			return DATAFLASH_ERROR;
-
-		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
-		if(!status)
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-
-		/* Update size, source and destination pointers */
-		size -= pDataFlash->pDevice->pages_size ;
-		dest += pDataFlash->pDevice->pages_size ;
-		src  += pDataFlash->pDevice->pages_size ;
-	}
-
-	/* If still some bytes to read */
-	if ( size > 0 ) {
-		/* program dataflash page */
-		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
-			return DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
-	}
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashRead 					*/
-/* Object              : Read a block in dataflash				*/
-/* Input Parameters    : 							*/
-/* Return value		: 							*/
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
-	AT91PS_DataFlash pDataFlash,
-	unsigned long addr,
-	unsigned long size,
-	char *buffer)
-{
-	unsigned long SizeToRead;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
-		return -1;
-
-	while (size) {
-		SizeToRead = (size < 0x8000)? size:0x8000;
-
-		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
-			return -1;
-
-		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
-			return -1;
-
-		size -= SizeToRead;
-		addr += SizeToRead;
-		buffer += SizeToRead;
-	}
-
-	return DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataflashProbe 					*/
-/* Object              : 							*/
-/* Input Parameters    : 							*/
-/* Return value	       : Dataflash status register				*/
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
-	AT91F_SpiEnable(cs);
-	AT91F_DataFlashGetStatus(pDesc);
-	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
-}
-
-#endif

board/cobra5272/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o
+COBJS	= $(BOARD).o flash.o mii.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/cobra5272/cobra5272.c

@@ -22,8 +22,7 @@
  */
 
 #include <common.h>
-#include <asm/m5272.h>
+#include <asm/immap.h>
-#include <asm/immap_5272.h>
 
 
 int checkboard (void)
@@ -35,7 +34,7 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-	volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 
 	sdp->sdram_sdtr = 0xf539;
 	sdp->sdram_sdcr = 0x4211;

board/cobra5272/mii.c

@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fec.h>
+#include <asm/immap.h>
+
+#include <config.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#undef MII_DEBUG
+#undef ET_DEBUG
+
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+	} else {
+	}
+	return 0;
+}
+
+#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+
+/* Make MII read/write commands for the FEC. */
+#define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
+
+#define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
+
+/* PHY identification */
+#define PHY_ID_LXT970		0x78100000	/* LXT970 */
+#define PHY_ID_LXT971		0x001378e0	/* LXT971 and 972 */
+#define PHY_ID_82555		0x02a80150	/* Intel 82555 */
+#define PHY_ID_QS6612		0x01814400	/* QS6612 */
+#define PHY_ID_AMD79C784	0x00225610	/* AMD 79C784 */
+#define PHY_ID_AMD79C874VC	0x0022561B	/* AMD 79C874 */
+#define PHY_ID_LSI80225		0x0016f870	/* LSI 80225 */
+#define PHY_ID_LSI80225B	0x0016f880	/* LSI 80225/B */
+#define PHY_ID_DP83848VV	0x20005C90	/* National 83848 */
+#define PHY_ID_DP83849		0x20005CA2	/* National 82849 */
+
+#define STR_ID_LXT970		"LXT970"
+#define STR_ID_LXT971		"LXT971"
+#define STR_ID_82555		"Intel82555"
+#define STR_ID_QS6612		"QS6612"
+#define STR_ID_AMD79C784	"AMD79C784"
+#define STR_ID_AMD79C874VC	"AMD79C874VC"
+#define STR_ID_LSI80225		"LSI80225"
+#define STR_ID_LSI80225B	"LSI80225/B"
+#define STR_ID_DP83848VV	"N83848"
+#define STR_ID_DP83849		"N83849"
+
+/****************************************************************************
+ * mii_init -- Initialize the MII for MII command without ethernet
+ * This function is a subset of eth_init
+ ****************************************************************************
+ */
+void mii_reset(struct fec_info_s *info)
+{
+	volatile fec_t *fecp = (fec_t *) (info->miibase);
+	int i;
+
+	fecp->ecr = FEC_ECR_RESET;
+	for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
+		udelay(1);
+	}
+	if (i == FEC_RESET_DELAY) {
+		printf("FEC_RESET_DELAY timeout\n");
+	}
+}
+
+/* send command to phy using mii, wait for result */
+uint mii_send(uint mii_cmd)
+{
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	volatile fec_t *ep;
+	uint mii_reply;
+	int j = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	ep = (fec_t *) info->miibase;
+
+	ep->mmfr = mii_cmd;	/* command to phy */
+
+	/* wait for mii complete */
+	while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
+		udelay(1);
+		j++;
+	}
+	if (j >= MCFFEC_TOUT_LOOP) {
+		printf("MII not complete\n");
+		return -1;
+	}
+
+	mii_reply = ep->mmfr;	/* result from phy */
+	ep->eir = FEC_EIR_MII;	/* clear MII complete */
+#ifdef ET_DEBUG
+	printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
+	       __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
+#endif
+
+	return (mii_reply & 0xffff);	/* data read from phy */
+}
+#endif				/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+
+#if defined(CFG_DISCOVER_PHY)
+int mii_discover_phy(struct eth_device *dev)
+{
+#define MAX_PHY_PASSES 11
+	struct fec_info_s *info = dev->priv;
+	int phyaddr, pass;
+	uint phyno, phytype;
+
+	if (info->phyname_init)
+		return info->phy_addr;
+
+	phyaddr = -1;		/* didn't find a PHY yet */
+	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
+		if (pass > 1) {
+			/* PHY may need more time to recover from reset.
+			 * The LXT970 needs 50ms typical, no maximum is
+			 * specified, so wait 10ms before try again.
+			 * With 11 passes this gives it 100ms to wake up.
+			 */
+			udelay(10000);	/* wait 10ms */
+		}
+
+		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+
+			phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
+#ifdef ET_DEBUG
+			printf("PHY type 0x%x pass %d type\n", phytype, pass);
+#endif
+			if (phytype != 0xffff) {
+				phyaddr = phyno;
+				phytype <<= 16;
+				phytype |=
+				    mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
+
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_AMD79C874VC:
+					strcpy(info->phy_name,
+					       STR_ID_AMD79C874VC);
+					info->phyname_init = 1;
+					break;
+				default:
+					strcpy(info->phy_name, "unknown");
+					info->phyname_init = 1;
+					break;
+				}
+
+#ifdef ET_DEBUG
+				printf("PHY @ 0x%x pass %d type ", phyno, pass);
+				switch (phytype & 0xffffffff) {
+				case PHY_ID_AMD79C874VC:
+					printf(STR_ID_AMD79C874VC);
+					break;
+				default:
+					printf("0x%08x\n", phytype);
+					break;
+				}
+#endif
+			}
+		}
+	}
+	if (phyaddr < 0)
+		printf("No PHY device found.\n");
+
+	return phyaddr;
+}
+#endif				/* CFG_DISCOVER_PHY */
+
+int mii_init(void) __attribute__((weak,alias("__mii_init")));
+
+void __mii_init(void)
+{
+	volatile fec_t *fecp;
+	struct fec_info_s *info;
+	struct eth_device *dev;
+	int miispd = 0, i = 0;
+	u16 autoneg = 0;
+
+	/* retrieve from register structure */
+	dev = eth_get_dev();
+	info = dev->priv;
+
+	fecp = (fec_t *) info->miibase;
+
+	fecpin_setclear(dev, 1);
+
+	mii_reset(info);
+
+	/* We use strictly polling mode only */
+	fecp->eimr = 0;
+
+	/* Clear any pending interrupt */
+	fecp->eir = 0xffffffff;
+
+	/* Set MII speed */
+	miispd = (gd->bus_clk / 1000000) / 5;
+	fecp->mscr = miispd << 1;
+
+	info->phy_addr = mii_discover_phy(dev);
+
+#define AUTONEGLINK		(PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
+	while (i < MCFFEC_TOUT_LOOP) {
+		autoneg = 0;
+		miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+		i++;
+
+		if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+			break;
+
+		udelay(500);
+	}
+	if (i >= MCFFEC_TOUT_LOOP) {
+		printf("Auto Negotiation not complete\n");
+	}
+
+	/* adapt to the half/full speed settings */
+	info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
+	info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
+}
+
+/*****************************************************************************
+ * Read and write a MII PHY register, routines used by MII Utilities
+ *
+ * FIXME: These routines are expected to return 0 on success, but mii_send
+ *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
+ *	  no PHY connected...
+ *	  For now always return 0.
+ * FIXME: These routines only work after calling eth_init() at least once!
+ *	  Otherwise they hang in mii_send() !!! Sorry!
+ *****************************************************************************/
+
+int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		       unsigned short *value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
+#endif
+	rdreg = mii_send(mk_mii_read(addr, reg));
+
+	*value = rdreg;
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", *value);
+#endif
+
+	return 0;
+}
+
+int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+			unsigned short value)
+{
+	short rdreg;		/* register working value */
+
+#ifdef MII_DEBUG
+	printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
+#endif
+
+	rdreg = mii_send(mk_mii_write(addr, reg, value));
+
+#ifdef MII_DEBUG
+	printf("0x%04x\n", value);
+#endif
+
+	return 0;
+}
+
+#endif				/* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */

board/davinci/dv-evm/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= dv_board.o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/davinci/dv-evm/board_init.S

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+
+	mov	pc, lr

board/davinci/dv-evm/config.mk

@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000

board/davinci/dv-evm/dv_board.c

@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_DAVINCI_EVM		901
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void	i2c_init(int speed, int slaveaddr);
+extern void	timer_init(void);
+extern int	eth_hw_init(void);
+extern phy_t	phy;
+
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p	mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01) {;}
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
+		(id == DAVINCI_LPSC_EMAC) ||
+		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+		(id == DAVINCI_LPSC_MDIO) ||
+		(id == DAVINCI_LPSC_USB) ||
+		(id == DAVINCI_LPSC_ATA) ||
+		(id == DAVINCI_LPSC_VLYNQ) ||
+		(id == DAVINCI_LPSC_UHPI) ||
+		(id == DAVINCI_LPSC_DDR_EMIF) ||
+		(id == DAVINCI_LPSC_AEMIF) ||
+		(id == DAVINCI_LPSC_MMC_SD) ||
+		(id == DAVINCI_LPSC_MEMSTICK) ||
+		(id == DAVINCI_LPSC_McBSP) ||
+		(id == DAVINCI_LPSC_GPIO)
+	   )
+	   	*mdctl |= 0x200;
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03) {;}
+	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+	int	i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+	/* Powerup the DSP */
+	dsp_on();
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	u_int8_t	tmp[20], buf[10];
+	int		i = 0;
+	int		clk = 0;
+
+	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
+	printf ("DDR Clock : %dMHz\n", (clk / 2));
+
+	/* Set Ethernet MAC address from EEPROM */
+	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
+		printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
+	} else {
+		tmp[0] = 0xff;
+		for (i = 0; i < 6; i++)
+			tmp[0] &= buf[i];
+
+		if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
+			sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
+				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+			setenv("ethaddr", (char *)&tmp[0]);
+		}
+	}
+
+	if (!eth_hw_init()) {
+		printf("ethernet init failed!\n");
+	} else {
+		printf("ETH PHY   : %s\n", phy.name);
+	}
+
+	i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
+
+	setenv ("videostd", ((i  & 0x80) ? "pal" : "ntsc"));
+
+	return(0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return(0);
+}

board/davinci/dv-evm/u-boot.lds

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/davinci/schmoogie/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= dv_board.o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/davinci/schmoogie/board_init.S

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+
+	mov	pc, lr

board/davinci/schmoogie/config.mk

@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000

board/davinci/schmoogie/dv_board.c

@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_SCHMOOGIE		1255
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void	i2c_init(int speed, int slaveaddr);
+extern void	timer_init(void);
+extern int	eth_hw_init(void);
+extern phy_t	phy;
+
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p	mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01) {;}
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
+		(id == DAVINCI_LPSC_EMAC) ||
+		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+		(id == DAVINCI_LPSC_MDIO) ||
+		(id == DAVINCI_LPSC_USB) ||
+		(id == DAVINCI_LPSC_ATA) ||
+		(id == DAVINCI_LPSC_VLYNQ) ||
+		(id == DAVINCI_LPSC_UHPI) ||
+		(id == DAVINCI_LPSC_DDR_EMIF) ||
+		(id == DAVINCI_LPSC_AEMIF) ||
+		(id == DAVINCI_LPSC_MMC_SD) ||
+		(id == DAVINCI_LPSC_MEMSTICK) ||
+		(id == DAVINCI_LPSC_McBSP) ||
+		(id == DAVINCI_LPSC_GPIO)
+	   )
+	   	*mdctl |= 0x200;
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03) {;}
+	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+	int	i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+	/* Powerup the DSP */
+	dsp_on();
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	u_int8_t	tmp[20], buf[10];
+	int		i = 0;
+	int		clk = 0;
+
+	/* Set serial number from UID chip */
+	u_int8_t	crc_tbl[256] = {
+			0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
+			0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
+			0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+			0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
+			0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
+			0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+			0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
+			0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
+			0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+			0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
+			0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
+			0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+			0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
+			0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
+			0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+			0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
+			0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
+			0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+			0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
+			0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
+			0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+			0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
+			0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
+			0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+			0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
+			0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
+			0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+			0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
+			0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
+			0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+			0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
+			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
+		};
+
+	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
+	printf ("DDR Clock : %dMHz\n", (clk / 2));
+
+	/* Set serial number from UID chip */
+	if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
+		printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+		forceenv("serial#", "FAILED");
+	} else {
+		if (buf[0] != 0x70) {	/* Device Family Code */
+			printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+			forceenv("serial#", "FAILED");
+		}
+	}
+	/* Now check CRC */
+	tmp[0] = 0;
+	for (i = 0; i < 8; i++)
+		tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
+
+	if (tmp[0] != 0) {
+		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR);
+		forceenv("serial#", "FAILED");
+	} else {
+		/* CRC OK, set "serial" env variable */
+		sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
+			buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
+		forceenv("serial#", (char *)&tmp[0]);
+	}
+
+	if (!eth_hw_init()) {
+		printf("ethernet init failed!\n");
+	} else {
+		printf("ETH PHY   : %s\n", phy.name);
+	}
+
+	return(0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return(0);
+}

board/davinci/schmoogie/u-boot.lds

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/davinci/sonata/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= dv_board.o
+SOBJS	:= board_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/davinci/sonata/board_init.S

@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
+ * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
+ * Visioneering if they reinvented the wheel once again to make sure :)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	dv_board_init
+dv_board_init:
+#ifdef SONATA_BOARD_GPIOWP
+	/* Set PINMUX0 to enable GPIO4 */
+	ldr	r0, _PINMUX0
+	ldr	r1, GPIO4_EN_MASK
+	ldr	r2, [r0]
+	and	r2, r2, r1
+	str	r2, [r0]
+
+	/* Enable GPIO LPSC module */
+	ldr	r0, PTSTAT
+
+gpio_ptstat_loop1:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop1
+
+	ldr	r1, MDCTL_GPIO
+	ldr	r2, [r1]
+	and	r2, r2, $0xfffffff8
+	orr	r2, r2, $0x00000003
+	str	r2, [r1]
+
+	orr	r2, r2, $0x00000200
+	str	r2, [r1]
+
+	ldr	r1, PTCMD
+	mov	r2, $0x00000001
+	str	r2, [r1]
+
+gpio_ptstat_loop2:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop2
+
+	ldr	r0, MDSTAT_GPIO
+gpio_mdstat_loop:
+	ldr	r2, [r0]
+	and	r2, r2, $0x0000001f
+	teq	r2, $0x00000003
+	bne	gpio_mdstat_loop
+
+	/* GPIO4 -> output */
+	ldr	r0, GPIO_DIR01
+	mov	r1, $0x10
+	ldr	r2, [r0]
+	bic	r2, r2, r0
+	str	r2, [r0]
+
+	/* Set it to 0 (Write Protect) */
+	ldr	r0, GPIO_CLR_DATA01
+	str	r1, [r0]
+#endif
+
+	mov	pc, lr
+
+#ifdef SONATA_BOARD_GPIOWP
+.ltorg
+
+GPIO4_EN_MASK:
+	.word	0xf77fffff
+MDCTL_GPIO:
+	.word	0x01c41a68
+MDSTAT_GPIO:
+	.word	0x01c41868
+GPIO_DIR01:
+	.word	0x01c67010
+GPIO_CLR_DATA01:
+	.word	0x01c6701c
+#endif

board/davinci/sonata/config.mk

@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000

board/davinci/sonata/dv_board.c

@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_SONATA		1254
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void	i2c_init(int speed, int slaveaddr);
+extern void	timer_init(void);
+extern int	eth_hw_init(void);
+extern phy_t	phy;
+
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p	mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01) {;}
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
+		(id == DAVINCI_LPSC_EMAC) ||
+		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+		(id == DAVINCI_LPSC_MDIO) ||
+		(id == DAVINCI_LPSC_USB) ||
+		(id == DAVINCI_LPSC_ATA) ||
+		(id == DAVINCI_LPSC_VLYNQ) ||
+		(id == DAVINCI_LPSC_UHPI) ||
+		(id == DAVINCI_LPSC_DDR_EMIF) ||
+		(id == DAVINCI_LPSC_AEMIF) ||
+		(id == DAVINCI_LPSC_MMC_SD) ||
+		(id == DAVINCI_LPSC_MEMSTICK) ||
+		(id == DAVINCI_LPSC_McBSP) ||
+		(id == DAVINCI_LPSC_GPIO)
+	   )
+	   	*mdctl |= 0x200;
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03) {;}
+	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+	int	i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+	/* Powerup the DSP */
+	dsp_on();
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	u_int8_t	tmp[20], buf[10];
+	int		i = 0;
+	int		clk = 0;
+
+
+	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
+	printf ("DDR Clock : %dMHz\n", (clk / 2));
+
+	/* Set Ethernet MAC address from EEPROM */
+	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
+		printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
+	} else {
+		tmp[0] = 0xff;
+		for (i = 0; i < 6; i++)
+			tmp[0] &= buf[i];
+
+		if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
+			sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
+				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+			setenv("ethaddr", (char *)&tmp[0]);
+		}
+	}
+
+	if (!eth_hw_init()) {
+		printf("ethernet init failed!\n");
+	} else {
+		printf("ETH PHY   : %s\n", phy.name);
+	}
+
+	return(0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return(0);
+}

board/davinci/sonata/u-boot.lds

@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/esd/ash405/Makefile

@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/ash405/ash405.c

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -33,6 +34,7 @@
 #endif
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
 
 /* fpga configuration data - gzip compressed and generated by bin2c */
 const unsigned char fpgadata[] =
@@ -164,17 +166,11 @@ int misc_init_r (void)
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
 	udelay(1000); /* wait 1ms */
 
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
 	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
@@ -218,35 +214,17 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
 /* ------------------------------------------------------------------------- */
 
-int testdram (void)
+void reset_phy(void)
 {
-	/* TODO: XXX XXX XXX */
+#ifdef CONFIG_LXT971_NO_SLEEP
-	printf ("test: 16 MB - ok\n");
+	/*
-
+	 * Disable sleep mode in LXT971
-	return (0);
+	 */
-}
+	lxt971_no_sleep();
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
 #endif
+}

board/esd/cms700/Makefile

@@ -33,7 +33,10 @@ CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/cms700/cms700.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -68,9 +69,9 @@ int board_early_init_f (void)
 	/*
 	 * Reset CPLD via GPIO12 (CS3) pin
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
 
 	return 0;
@@ -94,13 +95,7 @@ int misc_init_r (void)
  	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
-
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
 
 	return (0);
 }
@@ -153,11 +148,6 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
@@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
 			break;
 		}
 	}
@@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP

board/esd/common/auto_update.c

@@ -24,14 +24,12 @@
 
 #include <common.h>
 
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
-#endif
-
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
+#if defined(CFG_NAND_LEGACY)
 #include <linux/mtd/nand_legacy.h>
+#endif
 #include <fat.h>
 #include <part.h>
 
@@ -294,6 +292,8 @@ int au_do_update(int i, long sz)
 			rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
 				     start, nbytes, (size_t *)&total, (uchar *)addr);
 			debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#else
+			rc = -1;
 #endif
 		}
 		if (rc != 0) {

board/esd/common/esd405ep_nand.c

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch(cmd) {
+	case NAND_CTL_SETCLE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+		break;
+	case NAND_CTL_CLRCLE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+		break;
+	case NAND_CTL_SETALE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+		break;
+	case NAND_CTL_CLRALE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+		break;
+	case NAND_CTL_SETNCE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+		break;
+	case NAND_CTL_CLRNCE:
+		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+		break;
+	}
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+	if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+		return 1;
+	return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+	/*
+	 * Set NAND-FLASH GPIO signals to defaults
+	 */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Initialize nand_chip structure
+	 */
+	nand->hwcontrol = esd405ep_nand_hwcontrol;
+	nand->dev_ready = esd405ep_nand_device_ready;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->chip_delay = NAND_BIG_DELAY_US;
+	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
+}
+#endif

board/esd/cpci750/cpci750.c

@@ -55,6 +55,71 @@
 #define DP(x)
 #endif
 
+static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
+				     {"PCI0DLL_1     "},  /* 30 */
+				     {"PCI0DLL_0     "},  /* 29 */
+				     {"PCI1DLL_2     "},  /* 28 */
+				     {"PCI1DLL_1     "},  /* 27 */
+				     {"PCI1DLL_0     "},  /* 26 */
+				     {"BbEP2En       "},  /* 25 */
+				     {"SDRAMRdDataDel"},  /* 24 */
+				     {"SDRAMRdDel    "},  /* 23 */
+				     {"SDRAMSync     "},  /* 22 */
+				     {"SDRAMPipeSel_1"},  /* 21 */
+				     {"SDRAMPipeSel_0"},  /* 20 */
+				     {"SDRAMAddDel   "},  /* 19 */
+				     {"SDRAMClkSel   "},  /* 18 */
+				     {"Reserved(1!)  "},  /* 17 */
+				     {"PCIRty        "},  /* 16 */
+				     {"BootCSWidth_1 "},  /* 15 */
+				     {"BootCSWidth_0 "},  /* 14 */
+				     {"PCI1PadsCal   "},  /* 13 */
+				     {"PCI0PadsCal   "},  /* 12 */
+				     {"MultiMVId_1   "},  /* 11 */
+				     {"MultiMVId_0   "},  /* 10 */
+				     {"MultiGTEn     "},  /* 09 */
+				     {"Int60xArb     "},  /* 08 */
+				     {"CPUBusConfig_1"},  /* 07 */
+				     {"CPUBusConfig_0"},  /* 06 */
+				     {"DefIntSpc     "},  /* 05 */
+				     {0               },  /* 04 */
+				     {"SROMAdd_1     "},  /* 03 */
+				     {"SROMAdd_0     "},  /* 02 */
+				     {"DRAMPadCal    "},  /* 01 */
+				     {"SInitEn       "},  /* 00 */
+				     {0               },  /* 31 */
+				     {0               },  /* 30 */
+				     {0               },  /* 29 */
+				     {0               },  /* 28 */
+				     {0               },  /* 27 */
+				     {0               },  /* 26 */
+				     {0               },  /* 25 */
+				     {0               },  /* 24 */
+				     {0               },  /* 23 */
+				     {0               },  /* 22 */
+				     {"JTAGCalBy     "},  /* 21 */
+				     {"GB2Sel        "},  /* 20 */
+				     {"GB1Sel        "},  /* 19 */
+				     {"DRAMPLL_MDiv_5"},  /* 18 */
+				     {"DRAMPLL_MDiv_4"},  /* 17 */
+				     {"DRAMPLL_MDiv_3"},  /* 16 */
+				     {"DRAMPLL_MDiv_2"},  /* 15 */
+				     {"DRAMPLL_MDiv_1"},  /* 14 */
+				     {"DRAMPLL_MDiv_0"},  /* 13 */
+				     {"GB0Sel        "},  /* 12 */
+				     {"DRAMPLLPU     "},  /* 11 */
+				     {"DRAMPLL_HIKVCO"},  /* 10 */
+				     {"DRAMPLLNP     "},  /* 09 */
+				     {"DRAMPLL_NDiv_7"},  /* 08 */
+				     {"DRAMPLL_NDiv_6"},  /* 07 */
+				     {"CPUPadCal     "},  /* 06 */
+				     {"DRAMPLL_NDiv_5"},  /* 05 */
+				     {"DRAMPLL_NDiv_4"},  /* 04 */
+				     {"DRAMPLL_NDiv_3"},  /* 03 */
+				     {"DRAMPLL_NDiv_2"},  /* 02 */
+				     {"DRAMPLL_NDiv_1"},  /* 01 */
+				     {"DRAMPLL_NDiv_0"}}; /* 00 */
+
 extern void flush_data_cache (void);
 extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
@@ -901,21 +966,37 @@ void board_prebootm_init ()
 	dcache_disable ();
 }
 
-
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	unsigned int reset_sample_low;
 	unsigned int reset_sample_high;
+	unsigned int l, l1, l2;
 
 	GT_REG_READ(0x3c4, &reset_sample_low);
 	GT_REG_READ(0x3d4, &reset_sample_high);
 	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
 
+	l2 = 0;
+	for (l=0; l<63; l++) {
+		if (show_config_tab[l][0] != 0) {
+			printf("%14s:%1x ", show_config_tab[l],
+			       ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+			l2++;
+			if ((l2 % 4) == 0)
+				printf("\n");
+		} else {
+			l1++;
+		}
+		if (l == 32)
+			reset_sample_low = reset_sample_high;
+	}
+	printf("\n");
+
 	return(0);
 }
 
 U_BOOT_CMD(
-	show_cfg,	1,	1,	do_show_cfg,
+	show_config,	1,	1,	do_show_config,
-	"show_cfg- Show Marvell strapping register\n",
+	"show_config - Show Marvell strapping register\n",
 	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
 	);

board/esd/cpci750/ide.c

@@ -43,6 +43,8 @@ int ide_preinit (void)
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
 	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn == -1)
+	        devbusfn = pci_find_device (0x1095, 0x3114, 0);
 	if (devbusfn != -1) {
 		status = 0;
 

board/esd/hh405/Makefile

@@ -28,7 +28,10 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/hh405/hh405.c

@@ -5,7 +5,7 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -476,12 +476,6 @@ int misc_init_r (void)
 	 */
 	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
 
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
 	/*
 	 * Reset touch-screen controller
 	 */
@@ -690,20 +684,6 @@ void ide_set_reset(int on)
 #endif /* CONFIG_IDE_RESET */
 
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state

board/esd/hub405/Makefile

@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/hub405/hub405.c

@@ -152,12 +152,6 @@ int misc_init_r (void)
 
 	out32(GPIO0_OR, val);
 
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
 	/*
 	 * check board type and setup AP power
 	 */
@@ -242,33 +236,5 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
-
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif

board/esd/plu405/Makefile

@@ -28,7 +28,10 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
+	../common/auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/plu405/plu405.c

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -31,6 +32,8 @@
 #define FPGA_DEBUG
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 extern void lxt971_no_sleep(void);
 
@@ -114,6 +117,10 @@ int misc_init_r (void)
 	int index;
 	int i;
 
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 	dst = malloc(CFG_FPGA_MAX_SIZE);
 	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
@@ -177,17 +184,11 @@ int misc_init_r (void)
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
 	udelay(1000); /* wait 1ms */
 
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
 	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
@@ -226,24 +227,10 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
 
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
@@ -262,31 +249,6 @@ void ide_set_reset(int on)
 #endif /* CONFIG_IDE_RESET */
 
 
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active)
-{
-	if (au_active) {
-		printf("\n Dies ist die board-funktion: Updating!!!\n");
-	} else {
-		printf("\n Dies ist die board-funktion: Updating done!!!\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP

board/esd/voh405/Makefile

@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/voh405/voh405.c

@@ -194,12 +194,6 @@ int misc_init_r (void)
 	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
 	/*
 	 * Enable interrupts in exar duart mcr[3]
 	 */
@@ -340,17 +334,3 @@ void ide_set_reset(int on)
 	}
 }
 #endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif

board/esd/wuh405/Makefile

@@ -28,7 +28,9 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))