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x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer

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At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2017-05-31 01:04:15 -07:00
parent 5e74e5a682
commit f8f291b096
9 changed files with 39 additions and 28 deletions
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11
arch/x86/cpu/baytrail/fsp_configs.c
View file

@ -175,9 +175,10 @@ void update_fsp_configs(struct fsp_config_data *config,
fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
"fsp,enable-azalia");
fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe");
fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node,
"fsp,lpss-sio-enable-pci-mode");
fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
LPE_MODE_PCI);
fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode",
LPSS_SIO_MODE_PCI);
fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
@ -199,8 +200,8 @@ void update_fsp_configs(struct fsp_config_data *config,
fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
"fsp,mrc-debug-msg");
fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node,
"fsp,scc-enable-pci-mode");
fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode",
SCC_MODE_PCI);
fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
"fsp,igd-render-standby");
fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,

6
arch/x86/dts/bayleybay.dts
View file

@ -248,8 +248,8 @@
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@ -264,7 +264,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;

4
arch/x86/dts/baytrail_som-db5800-som-6867.dts
View file

@ -268,7 +268,7 @@
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-azalia;
fsp,lpss-sio-enable-pci-mode;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@ -283,7 +283,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,enable-igd;
};

6
arch/x86/dts/conga-qeval20-qa3-e3845.dts
View file

@ -258,8 +258,8 @@
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-pwm0;
@ -267,7 +267,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;

6
arch/x86/dts/dfi-bt700.dtsi
View file

@ -261,8 +261,8 @@
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@ -277,7 +277,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;

6
arch/x86/dts/minnowmax.dts
View file

@ -272,8 +272,8 @@
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@ -288,7 +288,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;

10
arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
View file

@ -93,4 +93,14 @@ struct fspinit_rtbuf {
#define DIMM_SIDES_1RANKS 0
#define DIMM_SIDES_2RANKS 1
#define LPE_MODE_DISABLED 0
#define LPE_MODE_PCI 1
#define LPE_MODE_ACPI 2
#define LPSS_SIO_MODE_ACPI 0
#define LPSS_SIO_MODE_PCI 1
#define SCC_MODE_ACPI 0
#define SCC_MODE_PCI 1
#endif /* __FSP_CONFIGS_H__ */

6
arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
View file

@ -47,8 +47,8 @@ struct __packed upd_region {
uint8_t enable_azalia; /* Offset 0x002f */
uint32_t azalia_config_ptr; /* Offset 0x0030 */
uint8_t enable_xhci; /* Offset 0x0034 */
uint8_t enable_lpe; /* Offset 0x0035 */
uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
uint8_t lpe_mode; /* Offset 0x0035 */
uint8_t lpss_sio_mode; /* Offset 0x0036 */
uint8_t enable_dma0; /* Offset 0x0037 */
uint8_t enable_dma1; /* Offset 0x0038 */
uint8_t enable_i2_c0; /* Offset 0x0039 */
@ -67,7 +67,7 @@ struct __packed upd_region {
uint8_t reserved2[5]; /* Offset 0x0046 */
uint8_t mrc_debug_msg; /* Offset 0x004b */
uint8_t isp_enable; /* Offset 0x004c */
uint8_t scc_enable_pci_mode; /* Offset 0x004d */
uint8_t scc_mode; /* Offset 0x004d */
uint8_t igd_render_standby; /* Offset 0x004e */
uint8_t txe_uma_enable; /* Offset 0x004f */
uint8_t os_selection; /* Offset 0x0050 */

12
doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
View file

@ -19,8 +19,6 @@ is matched up to Intel's E3800 FSPv4 release.
- fsp,enable-sata
- fsp,enable-azalia
- fsp,enable-xhci
- fsp,enable-lpe
- fsp,lpss-sio-enable-pci-mode
- fsp,enable-dma0
- fsp,enable-dma1
- fsp,enable-i2-c0
@ -35,7 +33,6 @@ is matched up to Intel's E3800 FSPv4 release.
- fsp,enable-hsi
- fsp,mrc-debug-msg
- fsp,isp-enable
- fsp,scc-enable-pci-mode
- fsp,igd-render-standby
- fsp,txe-uma-enable
- fsp,emmc45-ddr50-enabled
@ -57,9 +54,12 @@ discovered by the FSP and used to setup main memory.
- fsp,mrc-init-spd-addr2
- fsp,emmc-boot-mode
- fsp,sata-mode
- fsp,lpe-mode
- fsp,lpss-sio-mode
- fsp,igd-dvmt50-pre-alloc
- fsp,aperture-size
- fsp,gtt-size
- fsp,scc-mode
- fsp,os-selection
- fsp,emmc45-retune-timer-value
@ -110,8 +110,8 @@ Example (from MinnowMax Dual Core):
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
fsp,enable-lpe;
fsp,lpss-sio-enable-pci-mode;
fsp,lpe-mode = <LPE_MODE_PCI>;
fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@ -126,7 +126,7 @@ Example (from MinnowMax Dual Core):
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
fsp,scc-enable-pci-mode;
fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;