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pci: mpc85xx: Allow 8/16-bit access to PCI config space

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This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read
and write access to PCI config space as described in more Freescale
reference manuals.

This change fixes issue that 8-bit and 16-bit write to PCI config space
caused to clear adjacent bits of 32-bit PCI register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Pali Rohár 2023-04-13 22:41:45 +02:00 committed by Tom Rini
parent 76c72930f9
commit f5375a4500
1 changed files with 24 additions and 2 deletions
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26
drivers/pci/pci_mpc85xx.c
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@ -25,7 +25,18 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr); out_be32(priv->cfg_addr, addr);
sync(); sync();
*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
switch (size) {
case PCI_SIZE_8:
*value = in_8(priv->cfg_data + (offset & 3));
break;
case PCI_SIZE_16:
*value = in_le16(priv->cfg_data + (offset & 2));
break;
case PCI_SIZE_32:
*value = in_le32(priv->cfg_data);
break;
}
return 0; return 0;
} }
@ -40,7 +51,18 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr); out_be32(priv->cfg_addr, addr);
sync(); sync();
out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
switch (size) {
case PCI_SIZE_8:
out_8(priv->cfg_data + (offset & 3), value);
break;
case PCI_SIZE_16:
out_le16(priv->cfg_data + (offset & 2), value);
break;
case PCI_SIZE_32:
out_le32(priv->cfg_data, value);
break;
}
sync(); sync();
return 0; return 0;