mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
f51697316a
8 changed files with 55 additions and 171 deletions
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@ -277,87 +277,6 @@ int board_early_init_f(void)
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return 0;
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}
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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/*----------------------------------------------------------------------------+
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| nand_reset.
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| Reset Nand flash
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| This routine will abort previous cmd
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+----------------------------------------------------------------------------*/
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int nand_reset(ulong addr)
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{
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int wait=0, stat=0;
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out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
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out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
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while ((stat != 0xc0) && (wait != 0xffff)) {
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stat = in8(addr + NAND_DATA_REG);
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wait++;
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}
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if (stat == 0xc0) {
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return 0;
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} else {
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printf("NAND Reset timeout.\n");
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return -1;
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}
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}
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void board_nand_set_device(int cs, ulong addr)
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{
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/* Set NandFlash Core Configuration Register */
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out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
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switch (cs) {
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case 1:
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/* -------
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* NAND0
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* -------
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* K9F1208U0A : 4 addr cyc, 1 col + 3 Row
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* Set NDF1CR - Enable External CS1 in NAND FLASH controller
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*/
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out32(addr + NAND_CR1_REG, 0x80002222);
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break;
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case 2:
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/* -------
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* NAND1
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* -------
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* K9K2G0B : 5 addr cyc, 2 col + 3 Row
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* Set NDF2CR : Enable External CS2 in NAND FLASH controller
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*/
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out32(addr + NAND_CR2_REG, 0xC0007777);
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break;
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}
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/* Perform Reset Command */
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if (nand_reset(addr) != 0)
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return;
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}
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void nand_init(void)
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{
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board_nand_set_device(1, CFG_NAND_ADDR);
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nand_probe(CFG_NAND_ADDR);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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#if 0 /* NAND1 not supported yet */
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board_nand_set_device(2, CFG_NAND2_ADDR);
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nand_probe(CFG_NAND2_ADDR);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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#endif
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}
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#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
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int checkboard(void)
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{
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char *s = getenv("serial#");
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@ -68,19 +68,7 @@ SECTIONS
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cpu/ppc4xx/start.o (.text)
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board/amcc/bamboo/init.o (.text)
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cpu/ppc4xx/kgdb.o (.text)
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cpu/ppc4xx/traps.o (.text)
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cpu/ppc4xx/interrupts.o (.text)
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cpu/ppc4xx/serial.o (.text)
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cpu/ppc4xx/cpu_init.o (.text)
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cpu/ppc4xx/speed.o (.text)
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common/dlmalloc.o (.text)
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lib_generic/crc32.o (.text)
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lib_ppc/extable.o (.text)
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lib_generic/zlib.o (.text)
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/* . = env_offset;*/
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/* common/environment.o(.text)*/
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board/amcc/bamboo/bamboo.o (.text)
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*(.text)
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*(.fixup)
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@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
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}
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#endif /* CONFIG_DDR_DATA_EYE */
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#if defined(CONFIG_NAND_SPL)
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/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
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* for the 4k NAND boot image so define bus_frequency to 133MHz here
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* which is save for the refresh counter setup.
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*/
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#define get_bus_freq(val) 133000000
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#endif
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/*************************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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@ -404,7 +412,7 @@ long int initdram (int board_type)
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mtsdram(DDR0_22, 0x00267F0B);
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01010002);
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if (speed > 133333333)
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if (speed > 133333334)
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mtsdram(DDR0_26, 0x5B26050C);
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else
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mtsdram(DDR0_26, 0x5B260408);
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@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
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{
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unsigned long zmiifer=0x0;
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unsigned long pfc1;
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/*
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* Right now only 2*RGMII is supported. Please extend when needed.
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* sr - 2006-08-29
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*/
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switch (1) {
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case 0:
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mfsdr(sdr_pfc1, pfc1);
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pfc1 &= SDR0_PFC1_SELECT_MASK;
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switch (pfc1) {
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case SDR0_PFC1_SELECT_CONFIG_2:
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/* 1 x GMII port */
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out32 (ZMII_FER, 0x00);
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out32 (RGMII_FER, 0x00000037);
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bis->bi_phymode[0] = BI_PHYMODE_GMII;
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bis->bi_phymode[1] = BI_PHYMODE_NONE;
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break;
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case 1:
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case SDR0_PFC1_SELECT_CONFIG_4:
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/* 2 x RGMII ports */
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out32 (ZMII_FER, 0x00);
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out32 (RGMII_FER, 0x00000055);
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bis->bi_phymode[0] = BI_PHYMODE_RGMII;
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bis->bi_phymode[1] = BI_PHYMODE_RGMII;
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break;
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case 2:
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case SDR0_PFC1_SELECT_CONFIG_6:
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/* 2 x SMII ports */
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out32 (ZMII_FER,
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((ZMII_FER_SMII) << ZMII_FER_V(0)) |
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((ZMII_FER_SMII) << ZMII_FER_V(1)));
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out32 (RGMII_FER, 0x00000000);
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bis->bi_phymode[0] = BI_PHYMODE_SMII;
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bis->bi_phymode[1] = BI_PHYMODE_SMII;
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break;
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case SDR0_PFC1_SELECT_CONFIG_1_2:
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/* only 1 x MII supported */
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out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
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out32 (RGMII_FER, 0x00000000);
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bis->bi_phymode[0] = BI_PHYMODE_MII;
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bis->bi_phymode[1] = BI_PHYMODE_NONE;
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break;
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default:
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break;
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2005-2006
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -43,7 +43,6 @@
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* 2nd ethernet port you have to "undef" the following define.
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*/
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#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
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#define CFG_NAND_LEGACY
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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@ -143,65 +142,13 @@
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NAND-FLASH related
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
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#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
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#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
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#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
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#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
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#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
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#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
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#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
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#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
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#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
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#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
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#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
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#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
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#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
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#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
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#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
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#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
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#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
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#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
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/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
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#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
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#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
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#define NAND0_CMD_READ2 0x50
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#define NAND0_CMD_READ_ID 0x90
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#define NAND0_CMD_READ_STATUS 0x70
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#define NAND0_CMD_RESET 0xFF
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#define NAND0_CMD_PAGE_PROG 0x80
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#define NAND0_CMD_PAGE_PROG_TRUE 0x10
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#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
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#define NAND0_CMD_BLOCK_ERASE 0x60
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#define NAND0_CMD_BLOCK_ERASE_END 0xD0
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
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#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
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#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
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#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
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/* not needed with 440EP NAND controller */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_CS 1
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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@ -360,7 +360,19 @@
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EBC_BXCR_BW_16BIT)
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/* Memory Bank 1 (Xilinx System ACE controller) initialization */
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#define CFG_EBC_PB1AP 0x7F8FFE80
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#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(4) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_NONDELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
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EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | \
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@ -38,7 +38,9 @@
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#define CONFIG_440GRX 1 /* Specific PPC440GRx */
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#endif
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
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/* Detect Sequoia PLL input clock automatically via CPLD bit */
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#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
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3333333 : 33000000)
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o init.o resetvec.o
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COBJS = nand_boot.o ndfc.o sdram.o speed.o
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COBJS = nand_boot.o ndfc.o sdram.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -69,10 +69,6 @@ $(obj)start.S:
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@rm -f $(obj)start.S
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ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
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$(obj)speed.c:
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@rm -f $(obj)speed.c
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ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
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# from board directory
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$(obj)init.S:
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@rm -f $(obj)init.S
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