fpga: Added Kconfig support for FPGA_SPARTAN3

This patch added Kconfig support for FPGA_SPARTAN3 and migrates the
values over to the defconfigs.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
This commit is contained in:
Vipul Kumar 2018-02-16 18:02:49 +05:30 committed by Tom Rini
parent d231182441
commit f415834608
9 changed files with 9 additions and 4 deletions

View file

@ -40,6 +40,7 @@ CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTP_HOSTNAME=y
CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTP_SUBNETMASK=y
CONFIG_FPGA_XILINX=y CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_MXC_GPIO=y CONFIG_MXC_GPIO=y
CONFIG_MMC_MXC=y CONFIG_MMC_MXC=y
CONFIG_NAND=y CONFIG_NAND=y

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@ -19,4 +19,5 @@ CONFIG_CMD_JFFS2=y
CONFIG_FPGA_ALTERA=y CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

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@ -32,6 +32,7 @@ CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTP_DNS=y CONFIG_BOOTP_DNS=y
CONFIG_FPGA_XILINX=y CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000 CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y CONFIG_NAND=y

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@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8 CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
CONFIG_FPGA_XILINX=y CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_I2C_DW=y CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set # CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_NOR_FLASH=y

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@ -45,4 +45,9 @@ config FPGA_ZYNQMPPL
Enable FPGA driver for loading bitstream in BIT and BIN format Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device. on Xilinx Zynq UltraScale+ (ZynqMP) device.
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
help
Enable Spartan3 FPGA driver for loading in BIT format.
endmenu endmenu

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@ -200,7 +200,6 @@
* FPGA * FPGA
*/ */
#define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC #define CONFIG_SYS_FPGA_CHECK_CTRLC

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@ -171,7 +171,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x20000 #define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000 #define CONFIG_SYS_FPGA_WAIT 1000

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@ -32,7 +32,6 @@
/* /*
* FPGA * FPGA
*/ */
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 10000 #define CONFIG_SYS_FPGA_WAIT 10000
#define CONFIG_MAX_FPGA_DEVICES 1 #define CONFIG_MAX_FPGA_DEVICES 1

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@ -85,7 +85,6 @@
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* FPGA config options */ /* FPGA config options */
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_COUNT 1
/* USB EHCI options */ /* USB EHCI options */