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https://github.com/AsahiLinux/u-boot
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Add MX25 support to nand_spl fsl nfc driver
MX25 has a different version of the fsl_nfc flash controller known as version 1.1. Add support to the nand_spl fsl_nfc driver Versioning differs from mainline mxc kernel driver no consensus yet on if the naming here and in Redboot or the kernel is "correct". Signed-off-by: John Rigby <jcrigby@gmail.com> Signed-off-by: Wolfgang Denk <wd@denx.de> CC: Scott Wood <scottwood@freescale.com>
This commit is contained in:
John Rigby
Scott Wood
parent
ef22b50370
commit
f3bb63a304
2 changed files with 131 additions and 27 deletions
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@ -1,5 +1,4 @@
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/*
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*
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* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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@ -25,21 +24,57 @@
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#define __FSL_NFC_H
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/*
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* TODO: Use same register defs for nand_spl mxc nand driver
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* and mtd mxc nand driver.
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*
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* Register map and bit definitions for the Freescale NAND Flash
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* Controller present in i.MX31 and other devices.
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* Controller present in various i.MX devices.
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*
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* MX31 and MX27 have version 1 which has
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* 4 512 byte main buffers and
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* 4 16 byte spare buffers
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* to support up to 2K byte pagesize nand.
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* Reading or writing a 2K page requires 4 FDI/FDO cycles.
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*
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* MX25 has version 1.1 which has
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* 8 512 byte main buffers and
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* 8 64 byte spare buffers
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* to support up to 4K byte pagesize nand.
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* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
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* Also some of registers are moved and/or changed meaning as seen below.
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*/
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#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
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#define MXC_NFC_V1
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#elif defined(CONFIG_MX25)
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#define MXC_NFC_V1_1
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#else
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#warning "MXC NFC version not defined"
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#endif
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#if defined(MXC_NFC_V1)
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#define NAND_MXC_NR_BUFS 4
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#define NAND_MXC_SPARE_BUF_SIZE 16
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#define NAND_MXC_REG_OFFSET 0xe00
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#define NAND_MXC_2K_MULTI_CYCLE 1
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#elif defined(MXC_NFC_V1_1)
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#define NAND_MXC_NR_BUFS 8
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#define NAND_MXC_SPARE_BUF_SIZE 64
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#define NAND_MXC_REG_OFFSET 0x1e00
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#else
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#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
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#endif
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struct fsl_nfc_regs {
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u32 main_area0[128]; /* @0x000 */
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u32 main_area1[128];
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u32 main_area2[128];
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u32 main_area3[128];
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u32 spare_area0[4];
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u32 spare_area1[4];
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u32 spare_area2[4];
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u32 spare_area3[4];
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u32 reserved1[64 - 16 + 64 * 5];
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u16 bufsiz; /* @ 0xe00 */
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u32 main_area[NAND_MXC_NR_BUFS][512/4];
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u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
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/*
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* reserved size is offset of nfc registers
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* minus total main and spare sizes
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*/
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u8 reserved1[NAND_MXC_REG_OFFSET
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- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
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#if defined(MXC_NFC_V1)
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u16 bufsiz;
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u16 reserved2;
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u16 buffer_address;
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u16 flash_add;
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@ -54,6 +89,30 @@ struct fsl_nfc_regs {
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u16 nand_flash_wr_pr_st;
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u16 nand_flash_config1;
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u16 nand_flash_config2;
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#elif defined(MXC_NFC_V1_1)
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u16 reserved2[2];
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u16 buffer_address;
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u16 flash_add;
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u16 flash_cmd;
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u16 configuration;
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u16 ecc_status_result;
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u16 ecc_status_result2;
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u16 spare_area_size;
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u16 nf_wr_prot;
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u16 reserved3[2];
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u16 nand_flash_wr_pr_st;
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u16 nand_flash_config1;
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u16 nand_flash_config2;
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u16 reserved4;
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u16 unlock_start_blk_add0;
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u16 unlock_end_blk_add0;
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u16 unlock_start_blk_add1;
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u16 unlock_end_blk_add1;
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u16 unlock_start_blk_add2;
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u16 unlock_end_blk_add2;
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u16 unlock_start_blk_add3;
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u16 unlock_end_blk_add3;
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#endif
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};
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/*
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@ -98,6 +157,9 @@ struct fsl_nfc_regs {
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*/
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#define NFC_INT 0x8000
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#ifdef MXC_NFC_V1_1
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#define NFC_4_8N_ECC (1 << 0)
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#endif
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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@ -26,11 +26,15 @@
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#include <common.h>
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#include <nand.h>
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#ifdef CONFIG_MX31
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#include <asm-arm/arch/mx31-regs.h>
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#else
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#include <asm-arm/arch/imx-regs.h>
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#endif
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#include <asm/io.h>
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#include <fsl_nfc.h>
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static struct fsl_nfc_regs *nfc;
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struct fsl_nfc_regs *nfc;
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static void nfc_wait_ready(void)
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{
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@ -45,13 +49,35 @@ static void nfc_wait_ready(void)
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writew(tmp, &nfc->nand_flash_config2);
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}
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static void nfc_nand_init(void)
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void nfc_nand_init(void)
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{
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#if defined(MXC_NFC_V1_1)
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int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
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int config1;
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writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
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/* unlocking RAM Buff */
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writew(0x2, &nfc->configuration);
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/* hardware ECC checking and correct */
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config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
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/*
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* if spare size is larger that 16 bytes per 512 byte hunk
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* then use 8 symbol correction instead of 4
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*/
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if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
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config1 &= ~NFC_4_8N_ECC;
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else
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config1 |= NFC_4_8N_ECC;
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writew(config1, &nfc->nand_flash_config1);
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#elif defined(MXC_NFC_V1)
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/* unlocking RAM Buff */
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writew(0x2, &nfc->configuration);
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/* hardware ECC checking and correct */
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writew(NFC_ECC_EN, &nfc->nand_flash_config1);
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#endif
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}
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static void nfc_nand_command(unsigned short command)
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@ -65,12 +91,12 @@ static void nfc_nand_page_address(unsigned int page_address)
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{
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unsigned int page_count;
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writew(0x00, &nfc->flash_cmd);
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writew(0x00, &nfc->flash_add);
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writew(NFC_ADDR, &nfc->nand_flash_config2);
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nfc_wait_ready();
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/* code only for 2kb flash */
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if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) {
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/* code only for large page flash */
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if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
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writew(0x00, &nfc->flash_add);
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writew(NFC_ADDR, &nfc->nand_flash_config2);
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nfc_wait_ready();
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@ -88,22 +114,38 @@ static void nfc_nand_page_address(unsigned int page_address)
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page_count = page_count >> 8;
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} while (page_count);
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}
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writew(0x00, &nfc->flash_add);
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writew(NFC_ADDR, &nfc->nand_flash_config2);
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nfc_wait_ready();
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}
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static void nfc_nand_data_output(void)
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{
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int config1 = readw(&nfc->nand_flash_config1);
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#ifdef NAND_MXC_2K_MULTI_CYCLE
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int i;
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#endif
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config1 |= NFC_ECC_EN | NFC_INT_MSK;
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writew(config1, &nfc->nand_flash_config1);
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writew(0, &nfc->buffer_address);
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writew(NFC_OUTPUT, &nfc->nand_flash_config2);
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nfc_wait_ready();
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#ifdef NAND_MXC_2K_MULTI_CYCLE
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/*
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* The NAND controller requires four output commands for
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* large page devices.
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* This NAND controller requires multiple input commands
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* for pages larger than 512 bytes.
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*/
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for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
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writew(NFC_ECC_EN, &nfc->nand_flash_config1);
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writew(i, &nfc->buffer_address); /* read in i:th buffer */
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for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
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config1 = readw(&nfc->nand_flash_config1);
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config1 |= NFC_ECC_EN | NFC_INT_MSK;
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writew(config1, &nfc->nand_flash_config1);
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writew(i, &nfc->buffer_address);
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writew(NFC_OUTPUT, &nfc->nand_flash_config2);
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nfc_wait_ready();
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}
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#endif
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}
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static int nfc_nand_check_ecc(void)
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@ -121,7 +163,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
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nfc_nand_command(NAND_CMD_READ0);
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nfc_nand_page_address(page_address);
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if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
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if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
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nfc_nand_command(NAND_CMD_READSTART);
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nfc_nand_data_output(); /* fill the main buffer 0 */
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@ -129,7 +171,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
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if (nfc_nand_check_ecc())
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return -1;
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src = &nfc->main_area0[0];
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src = &nfc->main_area[0][0];
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dst = (u32 *)buf;
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/* main copy loop from NAND-buffer to SDRAM memory */
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@ -154,12 +196,12 @@ static int is_badblock(int pagenumber)
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nfc_nand_command(NAND_CMD_READ0);
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nfc_nand_page_address(page);
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if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
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if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
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nfc_nand_command(NAND_CMD_READSTART);
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nfc_nand_data_output(); /* fill the main buffer 0 */
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src = &nfc->spare_area0[0];
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src = &nfc->spare_area[0][0];
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/*
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* IMPORTANT NOTE: The nand flash controller uses a non-
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@ -209,7 +251,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
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if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
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/*
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* Yes, new block. See if this block is good. If not,
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* loop until we find i good block.
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* loop until we find a good block.
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*/
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while (is_badblock(page)) {
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page = page + CONFIG_SYS_NAND_PAGE_COUNT;
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